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公开(公告)号:US20210225933A1
公开(公告)日:2021-07-22
申请号:US16792271
申请日:2020-02-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Ya-Huei Tsai , Rai-Min Huang , Yu-Ping Wang , Hung-Yueh Chen
IPC: H01L27/22 , H01L23/528 , H01L43/02
Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region and a gate pattern extending from the first active region to the second active region, in which the gate pattern includes a H-shape according to a top view. Preferably, the gate pattern includes a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, and a third gate pattern connecting the first gate pattern and the second gate pattern along a second direction.
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公开(公告)号:US20210225414A1
公开(公告)日:2021-07-22
申请号:US17224153
申请日:2021-04-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Po-Kai Hsu , Hung-Yueh Chen , Kun-I Chou , Jing-Yin Jhang , Hui-Lin Wang , Yu-Ping Wang
Abstract: A MRAM structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with storage units on corresponding active areas, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.
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公开(公告)号:US20210184104A1
公开(公告)日:2021-06-17
申请号:US17182146
申请日:2021-02-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chung-Liang Chu , Jian-Cheng Chen , Yu-Ping Wang , Yu-Ruei Chen
Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.
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公开(公告)号:US20210111334A1
公开(公告)日:2021-04-15
申请号:US17131767
申请日:2020-12-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , Jing-Yin Jhang , I-Ming Tseng , Yu-Ping Wang , Chien-Ting Lin , Kun-Chen Ho , Yi-Syun Chou , Chang-Min Li , Yi-Wei Tseng , Yu-Tsung Lai , JUN XIE
Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
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公开(公告)号:US20210066579A1
公开(公告)日:2021-03-04
申请号:US16589083
申请日:2019-09-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Si-Han Tsai , Che-Wei Chang , Jing-Yin Jhang
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
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公开(公告)号:US10930839B2
公开(公告)日:2021-02-23
申请号:US16739060
申请日:2020-01-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chung-Liang Chu , Jian-Cheng Chen , Yu-Ping Wang , Yu-Ruei Chen
Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region comprises an octagon and the ring of MTJ region includes a first MTJ region and a second MTJ region extending along a first direction, a third MTJ region and a fourth MTJ region extending along a second direction, a fifth MTJ region and a sixth MTJ region extending along a third direction, and a seventh MTJ region and an eighth MTJ region extending along a fourth direction.
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公开(公告)号:US20210020828A1
公开(公告)日:2021-01-21
申请号:US16531129
申请日:2019-08-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , Jing-Yin Jhang , I-Ming Tseng , Yu-Ping Wang , Chien-Ting Lin , Kun-Chen Ho , Yi-Syun Chou , Chang-Min Li , Yi-Wei Tseng , Yu-Tsung Lai , JUN XIE
Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
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公开(公告)号:US20200373478A1
公开(公告)日:2020-11-26
申请号:US16438480
申请日:2019-06-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Chen-Yi Weng , Yi-Wei Tseng , Chin-Yang Hsieh , Jing-Yin Jhang , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Yu-Ping Wang
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.
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公开(公告)号:US20200176510A1
公开(公告)日:2020-06-04
申请号:US16214127
申请日:2018-12-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Chia-Chang Hsu , Chen-Yi Weng , Hung-Chan Lin , Jing-Yin Jhang , Yu-Ping Wang
IPC: H01L27/22 , G11C11/16 , H01L23/48 , H01L23/485 , H01L23/544 , H01L21/321 , H01L21/762 , H01L43/12
Abstract: The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.
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公开(公告)号:US10290723B2
公开(公告)日:2019-05-14
申请号:US15981913
申请日:2018-05-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chun-Tsen Lu , Chien-Ming Lai , Lu-Sheng Chou , Ya-Huei Tsai , Ching-Hsiang Chiu , Yu-Tung Hsiao , Chen-Ming Huang , Kun-Ju Li , Yu-Ping Wang
Abstract: A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.
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