公开(公告)号：US20200058669A1

公开(公告)日：2020-02-20

申请号：US16163274

申请日：2018-10-17

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Jun CHEN ,  Zhiliang XIA ,  Li Hong XIAO

IPC: H01L27/11573 ,  H01L27/1157 ,  H01L27/11582

Abstract: Embodiments of 3D memory devices and fabricating methods thereof are disclosed. The device comprises an array device semiconductor structure comprising an array interconnect layer disposed on the alternating conductor/dielectric stack and including a first interconnect structure. The device further comprises a peripheral device semiconductor structure comprising a peripheral interconnect layer disposed on a peripheral device and including a second interconnect structure. The device further comprises a pad embedded in the array device semiconductor structure or the peripheral interconnect layer, and a pad opening exposing a surface of the pad. The array interconnect layer is bonded with the peripheral interconnect layer, and the pad is electrically connected with the peripheral device through the first interconnect structure or the second interconnect structure.

公开(公告)号：US20190157082A1

公开(公告)日：2019-05-23

申请号：US16183174

申请日：2018-11-07

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Lu Ming FAN ,  Zi Qun HUA ,  Bi Feng LI ,  Qingchen CAO ,  Yaobin FENG ,  Zhiliang XIA ,  Zongliang HUO

IPC: H01L21/033 ,  H01L21/768

Abstract: A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer.

公开(公告)号：US20190043883A1

公开(公告)日：2019-02-07

申请号：US16046814

申请日：2018-07-26

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Qiang XU ,  Fandong LIU ,  Zongliang HUO ,  Zhiliang XIA ,  Yaohua YANG ,  Peizhen HONG ,  Wenyu HUA ,  Jia HE

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L27/11573 ,  H01L27/11568

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate, a first tier of conductor layers of a first length comprising a first plurality of conductor layers extending along a first direction over the substrate. The first direction is substantially parallel to a top surface of the substrate. In some embodiments, the memory device also includes at least one connection portion conductively connecting two or more conductor layers of the first tier, and a first metal contact via conductively shared by connected conductor layers of the first tier and connected to a first metal interconnect.