公开(公告)号：US20250157906A1

公开(公告)日：2025-05-15

申请号：US18399626

申请日：2023-12-28

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Hao ZHENG ,  Dongyu FAN ,  Tingting GAO ,  Lei LIU ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H10B80/00

Abstract: Systems, devices, and methods for fabricating semiconductor structures for semiconductor packaging are provided. One example method includes forming a stack of conductive layers interleaved with isolating layers in a redistribution layer (RDL) structure of a semiconductor device. First contact structures and second contact structures are formed in the RDL structure, where each of the first contact structures extends through a portion of the conductive layers and the isolating layers and is connected to a pad on a first interface of the RDL structure, each of the second contact structures is connected to a respective one of the first contact structures through one of the conductive layers, and each of the second contact structures is connected to a pad on a second interface of the RDL structure opposite to the first interface.

公开(公告)号：US20240339402A1

公开(公告)日：2024-10-10

申请号：US18382251

申请日：2023-10-20

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zhong ZHANG ,  Kun ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A memory device includes a stack structure and a first beam structure. The memory device includes array regions and an intermediate region arranged between the array regions in a first lateral direction. The stack structure includes a first block and a second block arranged in a second lateral direction. Each of the first block and the second block includes a wall-structure region. In the intermediate region, the wall-structure regions of the first block and the second block are separated by a staircase structure. The first beam structure is located in the intermediate region and extends along the second lateral direction. The first beam structure is connected to the wall-structure regions of the first block and the second block. The first beam structure includes first dielectric layers and electrode layers that are alternately stacked.

公开(公告)号：US20240304246A1

公开(公告)日：2024-09-12

申请号：US18124946

申请日：2023-03-22

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Jianquan JIA ,  Lei LIU ,  Lei JIN ,  Zhiliang XIA ,  Zongliang HUO

IPC: G11C16/10 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/10 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional (3D) memory device includes a memory string, a coarse top select gate (TSG) line configured to couple a coarse threshold voltage (Vth_coarse) for programming the memory string, a word line configured to program the memory string, a buffer TSG line configured to couple a buffer threshold voltage (Vth_buffer) for programming the memory string, a fine TSG line configured to couple a fine threshold voltage (Vth_fine) for programming the memory string, and a coarse TSG cut disposed between the memory string and a second memory string adjacent the memory string. The 3D memory device can intrinsically increase the coarse threshold voltage (Vth_coarse), decrease leakage current, dynamically adjust and fine tune a threshold voltage (Vth) of the memory string, and increase TSG reliability.

公开(公告)号：US20240282673A1

公开(公告)日：2024-08-22

申请号：US18643322

申请日：2024-04-23

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Linchun WU ,  Kun ZHANG ,  Zhong ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L23/48 ,  H01L21/48 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L23/481 ,  H01L21/4814 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes an insulating layer, a conductive layer stacking with the insulating layer and including a first conductive sublayer and a second conductive sublayer, a memory stack disposed on a side of the conductive layer away from the insulating layer, a spacer structure through the conductive layer, a contact structure in the spacer structure and extending vertically through the insulating layer, and a channel structure including a semiconductor channel. The contact structure includes a first contact portion and a second contact portion in contact with each other. A lateral cross-sectional area of the second contact portion is greater than a lateral cross-sectional area of the first contact portion. A portion of the semiconductor channel is in contact with the first conductive sublayer. The second conductive sublayer is disposed between the first conductive sublayer and the memory stack.

公开(公告)号：US20230354599A1

公开(公告)日：2023-11-02

申请号：US17731524

申请日：2022-04-28

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Tao Yang ,  Dongxue ZHAO ,  Yuancheng YANG ,  Lei LIU ,  Kun ZHANG ,  Di WANG ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zongliang HUO

IPC: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528

CPC classification number: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/5283

Abstract: A three-dimensional (3D) memory device includes a first memory cell, a second memory cell, a control gate between the first and second memory cells, a top contact coupled to the first memory cell, and a bottom contact coupled to the second memory cell. The first memory cell can include a first pillar, a first insulating layer surrounding the first pillar, a first gate contact coupled to a first word line, and a second gate contact coupled to a first plate line. The second memory cell can include a second pillar, a second insulating layer surrounding the second pillar, a third gate contact coupled to a second word line, and a fourth gate contact coupled to a second plate line. The 3D memory device can utilize dynamic flash memory (DFM), increase storage density, provide multi-cell storage, provide a three-state logic, decrease leakage current, increase retention time, and decrease refresh rates.

公开(公告)号：US20230354578A1

公开(公告)日：2023-11-02

申请号：US17731523

申请日：2022-04-28

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Di WANG ,  Lei LIU ,  Yuancheng YANG ,  Wenxi ZHOU ,  Kun ZHANG ,  Tao YANG ,  Dongxue ZHAO ,  Zhiliang XIA ,  Zongliang HUO

IPC: H01L27/108

CPC classification number: H01L27/10802

Abstract: A three-dimensional (3D) memory device includes a memory cell, a top contact coupled to the memory cell, and a bottom contact coupled to the memory cell. The memory cell can include a pillar, an insulating layer surrounding the pillar, a first gate contact surrounding a first portion of the insulating layer, and a second gate contact surrounding a second portion of the insulating layer. The pillar can be configured to store an electrical charge. The pillar can be a monocrystalline material. The 3D memory device can utilize dynamic flash memory (DFM), decrease defects, increase manufacturing efficiency, decrease leakage current, decrease junction current, decrease power consumption, increase storage density, increase charge retention times, and decrease refresh rates.

公开(公告)号：US20230284445A1

公开(公告)日：2023-09-07

申请号：US18316109

申请日：2023-05-11

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Qiang XU ,  Zhiliang XIA ,  Ping YAN ,  Guangji LI ,  Zongliang HUO

IPC: H10B43/20 ,  H01L21/762 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

CPC classification number: H10B43/20 ,  H01L21/762 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

Abstract: The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.

公开(公告)号：US20230086425A1

公开(公告)日：2023-03-23

申请号：US17993600

申请日：2022-11-23

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhongwang SUN ,  Guangji LI ,  Kun ZHANG ,  Ming HU ,  Jiwei CHENG ,  Shijin LUO ,  Kun BAO ,  Zhiliang XIA

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11529

Abstract: Embodiments of contact structures of a three-dimensional memory device and fabrication method thereof are disclosed. The three-dimensional memory structure includes a film stack disposed on a substrate, wherein the film stack includes a plurality of conductive and dielectric layer pairs, each conductive and dielectric layer pair having a conductive layer and a first dielectric layer. The three-dimensional memory structure also includes a staircase structure formed in the film stack, wherein the staircase structure includes a plurality of steps, each staircase step having two or more conductive and dielectric layer pairs. The three-dimensional memory structure further includes a plurality of coaxial contact structures formed in a first insulating layer over the staircase structure, wherein each coaxial contact structure includes one or more conductive and insulating ring pairs and a conductive core, each conductive and insulating ring pair having a conductive ring and an insulating ring.

公开(公告)号：US20220059564A1

公开(公告)日：2022-02-24

申请号：US17509891

申请日：2021-10-25

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Qiang XU ,  Fandong LIU ,  Zongliang HUO ,  Zhiliang XIA ,  Yaohua YANG ,  Peizhen HONG ,  Wenyu HUA ,  Jia HE

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11568 ,  H01L29/08 ,  H01L29/10

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device comprises a substrate, a stack structure on the substrate, and at least one gate line slit extending along a first direction substantially parallel to a top surface of the substrate, and dividing the stack structure into at least two portions. The stack structure includes at least one connection portion that divides the at least one gate line slit, and conductively connects the at least two portions.

公开(公告)号：US20220037490A1

公开(公告)日：2022-02-03

申请号：US17500340

申请日：2021-10-13

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zhongwang SUN ,  Zhong ZHANG ,  Lei LIU ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L29/423 ,  H01L27/11529 ,  H01L21/28 ,  H01L27/11573

Abstract: Memory device includes a bottom-select-gate (BSG) structure. Cut slits are formed vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.