公开(公告)号：US20200243557A1

公开(公告)日：2020-07-30

申请号：US16843714

申请日：2020-04-08

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Qiang XU ,  Fandong LIU ,  Zongliang HUO ,  Zhiliang XIA ,  Yaohua YANG ,  Peizhen HONG ,  Wenyu HUA ,  Jia HE

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11568 ,  H01L29/08 ,  H01L29/10

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the method comprises: providing a substrate; forming an alternating stack over the substrate, the alternating stack comprising a plurality of tiers of sacrificial layer/insulating layer pairs extending along a first direction substantially parallel to a top surface of the substrate; forming a plurality of tiers of word lines extending along the first direction based on the alternating stack; forming at least one connection portion conductively connecting two or more of the word lines of the plurality of tiers of word lines; and forming at least one metal contact via conductively shared by connected word lines, the at least one metal contact via being connected to at least one metal interconnect.

公开(公告)号：US20190081059A1

公开(公告)日：2019-03-14

申请号：US16046818

申请日：2018-07-26

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Qiang XU ,  Zhiliang XIA ,  Ping YAN ,  Guangji LI ,  Zongliang HUO

IPC: H01L27/11578 ,  H01L27/11565 ,  H01L27/1157

Abstract: The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.

公开(公告)号：US20200335514A1

公开(公告)日：2020-10-22

申请号：US16918683

申请日：2020-07-01

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Qiang XU ,  Zhiliang XIA ,  Ping YAN ,  Guangji LI ,  Zongliang HUO

IPC: H01L27/11578 ,  H01L27/11575 ,  H01L21/762 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.

公开(公告)号：US20190043883A1

公开(公告)日：2019-02-07

申请号：US16046814

申请日：2018-07-26

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Qiang XU ,  Fandong LIU ,  Zongliang HUO ,  Zhiliang XIA ,  Yaohua YANG ,  Peizhen HONG ,  Wenyu HUA ,  Jia HE

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L27/11573 ,  H01L27/11568

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate, a first tier of conductor layers of a first length comprising a first plurality of conductor layers extending along a first direction over the substrate. The first direction is substantially parallel to a top surface of the substrate. In some embodiments, the memory device also includes at least one connection portion conductively connecting two or more conductor layers of the first tier, and a first metal contact via conductively shared by connected conductor layers of the first tier and connected to a first metal interconnect.

公开(公告)号：US20230284445A1

公开(公告)日：2023-09-07

申请号：US18316109

申请日：2023-05-11

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Qiang XU ,  Zhiliang XIA ,  Ping YAN ,  Guangji LI ,  Zongliang HUO

IPC: H10B43/20 ,  H01L21/762 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

CPC classification number: H10B43/20 ,  H01L21/762 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

Abstract: The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.

公开(公告)号：US20220059564A1

公开(公告)日：2022-02-24

申请号：US17509891

申请日：2021-10-25

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Qiang XU ,  Fandong LIU ,  Zongliang HUO ,  Zhiliang XIA ,  Yaohua YANG ,  Peizhen HONG ,  Wenyu HUA ,  Jia HE

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11568 ,  H01L29/08 ,  H01L29/10

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device comprises a substrate, a stack structure on the substrate, and at least one gate line slit extending along a first direction substantially parallel to a top surface of the substrate, and dividing the stack structure into at least two portions. The stack structure includes at least one connection portion that divides the at least one gate line slit, and conductively connects the at least two portions.

公开(公告)号：US20190067323A1

公开(公告)日：2019-02-28

申请号：US16047158

申请日：2018-07-27

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Qiang XU ,  Zhiliang Xia ,  Ming Shao ,  Zongliang Huo

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/66833

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming an alternating dielectric stack on a substrate; forming multiple slits, each penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing multiple sacrificial layers in the alternating dielectric stack through the plurality of slits to form multiple trenches; forming a conductive layer in each of the trenches; forming a first isolation layer on sidewalls of the slits to cover the conductive layers to prevent the conductive layers from being oxidized; forming a second isolation layer on surfaces of the first isolation layer, a material of the second isolation layer being different from a material of the first isolation layer; and depositing a conductive material into the slits to form multiple conductive walls, the conductive walls are insulated from the conductive layers.