公开(公告)号：US20230068995A1

公开(公告)日：2023-03-02

申请号：US17875016

申请日：2022-07-27

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yuancheng Yang ,  Wenxi Zhou ,  Zhiliang Xia ,  Wei Liu ,  Zongliang Huo

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: The present disclosure relates to a three-dimensional (3D) memory and a fabrication method thereof. The method includes forming a memory chip on a first substrate, disposing a first semiconductor layer on the memory chip, forming a plurality of first contacts through the first semiconductor layer, forming a first peripheral circuit chip based on the first semiconductor layer, disposing a second semiconductor layer on the first peripheral circuit chip, forming a plurality of second contacts through the second semiconductor layer, and forming a second peripheral circuit chip based on the second semiconductor layer. The first peripheral circuit chip is electrically connected with the memory chip through the plurality of first contacts, and the second peripheral circuit chip is electrically connected with the memory chip through the plurality of first and second contacts.

公开(公告)号：US11562945B2

公开(公告)日：2023-01-24

申请号：US17020473

申请日：2020-09-14

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Linchun Wu ,  Kun Zhang ,  Zhong Zhang ,  Wenxi Zhou ,  Zhiliang Xia

IPC: H01L23/48 ,  H01L21/48 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: Embodiments of methods for forming contact structures and semiconductor devices thereof are disclosed. In an example, a semiconductor device includes an insulating layer, a conductive layer over the insulating layer, and a spacer structure in the conductive layer and in contact with the insulating layer. The semiconductor device also includes a first contact structure in the spacer structure and extending vertically through the insulating layer. The first contact structure includes a first contact portion and a second contact portion in contact with each other. An upper surface of the second contact portion is coplanar with an upper surface of the conductive layer.

公开(公告)号：US11557570B2

公开(公告)日：2023-01-17

申请号：US16913649

申请日：2020-06-26

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L27/11582 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L27/1157 ,  H01L27/11573

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer on a substrate, an N-type doped semiconductor layer on the sacrificial layer, and a dielectric stack on the N-type doped semiconductor layer are subsequently formed. A channel structure extending vertically through the dielectric stack and the N-type doped semiconductor layer is formed. The dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the N-type doped semiconductor layer. The substrate and the sacrificial layer are removed to expose an end of the channel structure. Part of the channel structure abutting the N-type doped semiconductor layer is replaced with a semiconductor plug.

公开(公告)号：US20230005865A1

公开(公告)日：2023-01-05

申请号：US17587656

申请日：2022-01-28

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Wei Liu ,  Liang Chen ,  Yanhong Wang ,  Zhiliang Xia ,  Yuancheng Yang

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A three-dimensional 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first semiconductor layer and an array of NAND memory strings. The second semiconductor structure is under a second side of the first semiconductor layer. The second side of the first semiconductor layer is opposite to the first side of the first semiconductor layer. The second semiconductor structure includes a second semiconductor layer, a first peripheral circuit, and a second peripheral circuit. The first peripheral circuit includes a first transistor in contact with a first side of the second semiconductor layer. The second peripheral circuit includes a second transistor in contact with a second side of the second semiconductor layer. The second side of the second semiconductor layer is opposite to the first side of the second semiconductor layer.

公开(公告)号：US20230005541A1

公开(公告)日：2023-01-05

申请号：US17480821

申请日：2021-09-21

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yuancheng Yang ,  Wenxi Zhou ,  Zhiliang Xia ,  Wei Liu

IPC: G11C16/04 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  G11C16/10 ,  G11C16/26

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of memory cells and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of memory cells including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of memory cells including a second transistor, and a third semiconductor layer in contact with the second transistor. The second semiconductor layer is between the first bonding interface and the first peripheral circuit. The third semiconductor layer is between the second bonding interface and the second peripheral circuit.

公开(公告)号：US11508750B2

公开(公告)日：2022-11-22

申请号：US16920201

申请日：2020-07-02

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Di Wang ,  Lei Liu ,  Wenxi Zhou ,  Zhiliang Xia

IPC: H01L27/11582 ,  H01L23/00 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a first semiconductor layer above the memory stack, a second semiconductor layer above and in contact with the first semiconductor layer, a plurality of channel structures each extending vertically through the memory stack and the first semiconductor layer, and an insulating structure extending vertically through the memory stack, the first semiconductor layer, and the second semiconductor layer.

公开(公告)号：US11289508B2

公开(公告)日：2022-03-29

申请号：US17081949

申请日：2020-10-27

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Wenyu Hua ,  Fandong Liu ,  Zhiliang Xia

IPC: H01L27/11582 ,  H01L23/535 ,  H01L29/08 ,  H01L29/10

Abstract: Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are provided. For example, a method for forming a 3D memory device is provided. A dielectric stack including interleaved sacrificial layers and dielectric layers is formed on a substrate. A staircase structure is formed on at least one side of the dielectric stack. Dummy channel holes and dummy source holes extending vertically through the staircase structure are formed. A subset of the dummy channel holes is surrounded by the dummy source holes. A dummy channel structure is formed in each dummy channel hole, and interleaved conductive layers and dielectric layers are formed in the staircase structure by replacing, through the dummy source holes, the sacrificial layers in the staircase structure with the conductive layers. A spacer is formed along a sidewall of each dummy source hole to cover the conductive layers in the staircase structure, and a contact is formed within the spacer in each dummy source hole.

公开(公告)号：US20220037352A1

公开(公告)日：2022-02-03

申请号：US17020457

申请日：2020-09-14

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack including interleaved stack conductive layers and stack dielectric layers, a semiconductor layer, a plurality of channel structures each extending vertically through the memory stack into the semiconductor layer, and an insulating structure extending vertically through the memory stack and including a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen.

公开(公告)号：US11239247B2

公开(公告)日：2022-02-01

申请号：US16900511

申请日：2020-06-12

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhongwang Sun ,  Rui Su ,  Zhong Zhang ,  Wenxi Zhou ,  Zhiliang Xia

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524

Abstract: Memory device includes a bottom-select-gate (BSG) structure including cut slits vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. A first gate-line slit is between first and second finger regions and includes gate-line sub-slits. The first finger region is divided into a first string region and a second string region by a first cut-slit, formed in the first finger region along a second lateral direction and further extended into at least the second finger region along the first lateral direction. At least one BSG defined by the first cut-slit is located in at least the second finger region to connect to cell strings in the first string region through an inter-portion between adjacent gate-line sub-slits.

公开(公告)号：US11233007B2

公开(公告)日：2022-01-25

申请号：US16944857

申请日：2020-07-31

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Di Wang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zhong Zhang

IPC: H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L21/768 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/1157

Abstract: Embodiments of 3D memory devices having staircase structures and methods for forming the same are disclosed. In an example, the 3D memory device includes a memory array structure and a staircase structure. The staircase structure is located in an intermediate of the memory array structure and divides the memory array structure into a first memory array structure and a second memory array structure along a lateral direction. The staircase structure includes a plurality of stairs extending along the lateral direction, and a bridge structure in contact with the memory array structure. The stairs include a stair above one or more dielectric pairs. The stair includes a conductor portion electrically connected to the bridge structure and is electrically connected to the memory array structure through the bridge structure. Along a second lateral direction perpendicular to the lateral direction and away from the bridge structure, a width of the conductor portion decreases.