公开(公告)号：US20120146236A1

公开(公告)日：2012-06-14

申请号：US12964823

申请日：2010-12-10

Applicant: Yaojian Lin ,  Kang Chen ,  Jianmin Fang

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang

IPC: H01L23/52 ,  H01L21/52 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/2101 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over a portion of the encapsulant within an interconnect site outside a footprint of the semiconductor die. An opening is formed through the first insulating layer within the interconnect site to expose the encapsulant. The opening can be ring-shaped or vias around the interconnect site and within a central region of the interconnect site to expose the encapsulant. A first conductive layer is formed over the first insulating layer to follow a contour of the first insulating layer. A second conductive layer is formed over the first conductive layer and exposed encapsulant. A second insulating layer is formed over the second conductive layer. A bump is formed over the second conductive layer in the interconnect site.

Abstract translation: 半导体器件具有安装到载体上的半导体管芯。 密封剂沉积在半导体管芯和载体上。 载体被移除。 第一绝缘层形成在半导体管芯的覆盖区之外的互连部位内的密封剂的一部分上。 通过互连部位内的第一绝缘层形成开口以露出密封剂。 开口可以是互连位置周围的环形或通孔，并且在互连位置的中心区域内以露出密封剂。 在第一绝缘层上形成第一导电层以遵循第一绝缘层的轮廓。 在第一导电层和暴露的密封剂上形成第二导电层。 第二绝缘层形成在第二导电层上。 在互连部位的第二导电层上形成凸点。

公开(公告)号：US20120126369A1

公开(公告)日：2012-05-24

申请号：US13365097

申请日：2012-02-02

Applicant: Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Robert C. Frye

Inventor： Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Robert C. Frye

IPC: H01L27/06 ,  H01L21/02

CPC classification number: H01L27/0794 ,  H01G4/228 ,  H01G4/33 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L27/016 ,  H01L28/40 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/73207 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/01074 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A passive device is formed on the substrate by depositing a first conductive layer over the substrate, depositing an insulating layer over the first conductive layer, and depositing a second conductive layer over the insulating layer. The passive device is a metal-insulator-metal capacitor. The deposition of the insulating layer and first and second conductive layers is performed without photolithography. An under bump metallization (UBM) layer is formed on the substrate in electrical contact with the plurality of active devices. A solder bump is formed over the UBM layer. The passive device can also be a resistor by depositing a resistive layer over the first conductive layer and depositing a third conductive layer over the resistive layer. The passive device electrically contacts the solder bump.

Abstract translation: 倒装芯片半导体器件具有在其上形成有多个有源器件的衬底。 通过在衬底上沉积第一导电层，在第一导电层上沉积绝缘层，以及在绝缘层上沉积第二导电层，在衬底上形成无源器件。 无源器件是金属 - 绝缘体 - 金属电容器。 绝缘层和第一和第二导电层的沉积在没有光刻的情况下进行。 在与多个有源器件电接触的衬底上形成凸块下金属化（UBM）层。 在UBM层上形成焊料凸块。 无源器件还可以是通过在第一导电层上沉积电阻层并在电阻层上沉积第三导电层的电阻器。 无源器件与焊料凸块电接触。

公开(公告)号：US08183095B2

公开(公告)日：2012-05-22

申请号：US13029936

申请日：2011-02-17

Applicant: Yaojian Lin ,  Kang Chen ,  Jianmin Fang ,  Xia Feng

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang ,  Xia Feng

IPC: H01L21/00

CPC classification number: H01L23/5389 ,  H01L21/31051 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49816 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/94 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2224/03

Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.

Abstract translation: 半导体晶片包含由锯条分隔开的多个半导体管芯。 在半导体晶片上形成绝缘层。 在绝缘层上形成保护层，该保护层包括沿着锯条的半导体管芯的边缘。 保护层覆盖半导体晶片的整个表面。 或者，在锯路上的保护层中形成开口。 绝缘层具有非平面表面，保护层具有平坦表面。 通过保护层和锯条将半导体晶片分离，以分离半导体管芯，同时保护半导体管芯的边缘。 与保护层一起，将半导体管芯安装到载体上。 密封剂沉积在半导体管芯和载体上。 去除载体和保护层。 在半导体管芯和密封剂上形成积层互连结构。

公开(公告)号：US20120104623A1

公开(公告)日：2012-05-03

申请号：US12914878

申请日：2010-10-28

Applicant: Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo

Inventor： Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo

IPC: H01L23/06 ,  H01L21/56

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L23/13 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1515 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/8091 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655

Abstract: A semiconductor substrate has a plurality of different size recesses formed in the substrate to provide a stepped interposer. A conductive via can be formed through the stepped interposer. An insulating layer follows a contour of the stepped interposer. A conductive layer is formed over the insulating layer following the contour of the stepped interposer. A first semiconductor die is partially disposed in a first recess and electrically connected to the conductive layer. A second semiconductor die is partially disposed in a second recess and electrically connected to the conductive layer. The first semiconductor die is electrically connected to the second semiconductor die through the conductive layer. The first and second semiconductor die can be flipchip type semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of the stepped interposer can be removed to reduce thickness.

Abstract translation: 半导体衬底具有形成在衬底中的多个不同尺寸的凹部以提供阶梯式插入器。 可以通过阶梯式内插器形成导电通孔。 绝缘层遵循阶梯式插入器的轮廓。 在阶梯式插入件的轮廓之后，在绝缘层之上形成导电层。 第一半导体管芯部分地设置在第一凹部中并电连接到导电层。 第二半导体管芯部分地设置在第二凹部中并电连接到导电层。 第一半导体管芯通过导电层与第二半导体管芯电连接。 第一和第二半导体管芯可以是倒装芯片型半导体管芯。 密封剂沉积在第一和第二半导体管芯上。 可以去除部分阶梯式内插器以减小厚度。

公开(公告)号：US08168470B2

公开(公告)日：2012-05-01

申请号：US12329789

申请日：2008-12-08

Applicant: Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

Inventor： Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

IPC: H01L21/00

CPC classification number: H01L23/147 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19106 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device is made with a conductive via formed through a top-side of the substrate. The conductive via extends vertically through less than a thickness of the substrate. An integrated passive device (IPD) is formed over the substrate. A plurality of first conductive pillars is formed over the first IPD. A first semiconductor die is mounted over the substrate. An encapsulant is formed around the first conductive pillars and first semiconductor die. A second IPD is formed over the encapsulant. An interconnect structure is formed over the second IPD. The interconnect structure operates as a heat sink. A portion of a back-side of the substrate is removed to expose the first conductive via. A second semiconductor die is mounted to the back-side of the substrate. The second semiconductor die is electrically connected to the first IPD and first semiconductor die through the conductive via.

Abstract translation: 半导体器件由通过衬底的顶侧形成的导电通孔制成。 导电通孔垂直延伸穿过小于衬底的厚度。 集成无源器件（IPD）形成在衬底上。 在第一IPD上形成多个第一导电柱。 第一半导体管芯安装在衬底上。 围绕第一导电柱和第一半导体管芯形成密封剂。 在密封剂上形成第二个IPD。 在第二IPD上形成互连结构。 互连结构作为散热器工作。 去除衬底的背面的一部分以露出第一导电通孔。 第二半导体管芯安装到衬底的背面。 第二半导体管芯通过导电通孔电连接到第一IPD和第一半导体管芯。

公开(公告)号：US20120056312A1

公开(公告)日：2012-03-08

申请号：US12874787

申请日：2010-09-02

Applicant: Reza A. Pagaila ,  Yaojian Lin ,  Seung Uk Yoon

Inventor： Reza A. Pagaila ,  Yaojian Lin ,  Seung Uk Yoon

IPC: H01L23/28 ,  H01L21/56

CPC classification number: H01L23/481 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/48 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/24225 ,  H01L2224/25171 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a TSV semiconductor wafer with a cavity formed in a first surface of the wafer. A second cavity can be formed in a second surface of the wafer. A plurality of semiconductor die is mounted within the cavities. The semiconductor die can be mounted side-by-side and/or stacked within the cavity. Conductive TSV can be formed through the die. An encapsulant is deposited within the cavity over the die. A CTE of the die is similar to a CTE of the encapsulant. A first interconnect structure is formed over a first surface of the encapsulant and wafer. A second interconnect structure is formed over a second surface of the encapsulant and wafer. The first and second interconnect structure are electrically connected to the TSV wafer. A second semiconductor die can be mounted over the first interconnect structure with encapsulant deposited over the second die.

Abstract translation: 半导体器件具有在晶片的第一表面中形成有腔的TSV半导体晶片。 可以在晶片的第二表面中形成第二空腔。 多个半导体管芯安装在空腔内。 半导体管芯可以并排安装和/或堆叠在腔内。 可以通过模具形成导电TSV。 密封剂沉积在模具内的空腔内。 模具的CTE类似于密封剂的CTE。 在密封剂和晶片的第一表面上形成第一互连结构。 在密封剂和晶片的第二表面上形成第二互连结构。 第一和第二互连结构电连接到TSV晶片。 第二半导体管芯可以安装在第一互连结构上，并且封装在第二管芯上。

公开(公告)号：US08120183B2

公开(公告)日：2012-02-21

申请号：US12763386

申请日：2010-04-20

Applicant: Yaojian Lin ,  Robert C. Frye

Inventor： Yaojian Lin ,  Robert C. Frye

IPC: H01L23/52

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105

Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.

Abstract translation: 一种制造半导体器件的方法包括提供具有设置在基板的顶表面上的第一导电层的基板。 在基板和第一导电层上形成高电阻率层。 介电层沉积在衬底，第一导电层和高电阻率层上。 介电层，高电阻率层和第一导电层的一部分形成电容器叠层。 在电介质层上形成第一钝化层。 在电容器堆叠和第一钝化层的一部分上形成第二导电层。 在电介质层中蚀刻第一开口以暴露高电阻率层的表面。 在电介质层中的第一开口和第一钝化层的一部分上沉积第三和第四导电层。

公开(公告)号：US20110254156A1

公开(公告)日：2011-10-20

申请号：US13172680

申请日：2011-06-29

Applicant: Yaojian Lin

Inventor： Yaojian Lin

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L21/6835 ,  H01L21/566 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of making a wafer level chip scale package includes providing a temporary substrate, and forming a wafer level interconnect structure over the temporary substrate using wafer level processes. The wafer level processes include forming a first insulating layer in contact with an upper surface of the temporary substrate, and forming a first conductive layer in contact with an upper surface of the first passivation layer. A first semiconductor die is mounted over the wafer level interconnect structure such that an active surface of the first semiconductor die is in electrical contact with the first conductive layer, and a first encapsulant is deposited over the first semiconductor die. A second encapsulant is deposited over the first encapsulant, and the first and second encapsulants are cured simultaneously. The temporary substrate is removed to expose the first passivation layer.

Abstract translation: 制造晶片级芯片级封装的方法包括提供临时衬底，以及使用晶片级工艺在临时衬底上形成晶片级互连结构。 晶片级工艺包括形成与临时衬底的上表面接触的第一绝缘层，以及形成与第一钝化层的上表面接触的第一导电层。 第一半导体管芯安装在晶片级互连结构上，使得第一半导体管芯的有源表面与第一导电层电接触，并且第一密封剂沉积在第一半导体管芯上。 第二密封剂沉积在第一密封剂上，并且第一和第二密封剂同时固化。 去除临时衬底以露出第一钝化层。

公开(公告)号：US20110204472A1

公开(公告)日：2011-08-25

申请号：US13098419

申请日：2011-04-30

Applicant: Reza A. Pagaila ,  Yaojian Lin

Inventor： Reza A. Pagaila ,  Yaojian Lin

IPC: H01L29/02 ,  H01L21/02 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/552 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/24195 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by mounting a semiconductor component over a carrier. A ferromagnetic inductor core is formed over the carrier. A pillar frame including a plurality of bodies is mounted over the carrier, semiconductor component, and inductor core. An encapsulant is deposited around the semiconductor component, plurality of bodies, and inductor core. A portion of the pillar frame is removed. A first remaining portion of the pillar frame bodies provide inductor pillars around the inductor core and a second remaining portion of the pillar frame bodies provide an interconnect pillar. A first interconnect structure is formed over a first surface of the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant. The first and second interconnect structures are electrically connected to the inductor pillars to form one or more 3D inductors.

Abstract translation: 通过在载体上安装半导体部件来制造半导体器件。 在载体上形成铁磁感应芯。 包括多个主体的支柱框架安装在载体，半导体部件和电感器芯上。 围绕半导体部件，多个主体和电感器芯体沉积密封剂。 取下柱框架的一部分。 柱框架体的第一剩余部分在电感器芯周围提供电感柱，并且柱框体的第二剩余部分提供互连柱。 在密封剂的第一表面上形成第一互连结构。 载体被移除。 在密封剂的第二表面上形成第二互连结构。 第一和第二互连结构电连接到电感器柱以形成一个或多个3D电感器。

公开(公告)号：US07968445B2

公开(公告)日：2011-06-28

申请号：US12651758

申请日：2010-01-04

Applicant: Yaojian Lin ,  Xu-Sheng Bao

Inventor： Yaojian Lin ,  Xu-Sheng Bao

IPC: H01L21/44

CPC classification number: H05K3/3452 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02123 ,  H01L2224/02163 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13011 ,  H01L2224/13016 ,  H01L2224/131 ,  H01L2224/1613 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K1/112 ,  H05K3/3436 ,  H05K3/3457 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/099 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/014

Abstract: A flip chip style semiconductor package has a substrate with a plurality of active devices formed thereon. A contact pad is formed over the substrate. An under bump metallization (UBM) layer is in electrical contact with the contact pad. A passivation layer is formed over the substrate. In one case, the UBM layer is disposed above the passivation layer. Alternatively, the passivation layer is disposed above the UBM layer. A portion of the passivation layer is removed to create a passivation island. The passivation island is centered with respect to the contact pad with its top surface devoid of the UBM layer. A solder bump is formed over the passivation island in electrical contact with the UBM layer. The passivation island forms a void in the solder bump for stress relief. The UBM layer may include a redistribution layer such that the passivation island is offset from the contact pad.

Abstract translation: 倒装片式半导体封装具有在其上形成有多个有源器件的衬底。 接触垫形成在衬底上。 凸块下金属化（UBM）层与接触焊盘电接触。 钝化层形成在衬底上。 在一种情况下，UBM层设置在钝化层上方。 或者，钝化层设置在UBM层上。 去除钝化层的一部分以产生钝化岛。 钝化岛相对于接触焊盘居中，其顶表面没有UBM层。 在与UBM层电接触的钝化岛上形成焊料凸点。 钝化岛在焊料凸块中形成空隙以消除应力。 UBM层可以包括再分布层，使得钝化岛从接触垫偏移。