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    Method of fabricating multi layer MEMS and microfluidic devices
    92.
    发明申请
    Method of fabricating multi layer MEMS and microfluidic devices 审中-公开
    制造多层MEMS和微流体装置的方法

    公开(公告)号：US20070105339A1

    公开(公告)日：2007-05-10

    申请号：US11406848

    申请日：2006-04-19

    Applicant: Sadeg Faris

    Inventor： Sadeg Faris

    IPC: H01L21/30

    CPC classification number: B81C1/00119 ,  B81B2201/058 ,  B81C1/00238 ,  B81C1/0038 ,  B81C2201/019 ,  G01R31/01 ,  H01L22/20 ,  H01L2224/13 ,  H01L2224/16 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

    Abstract: A method for fabricating multi layer microelectromechanical and microfluidic devices is disclosed. Multi layer microelectromechanical and microfluidic devices are fabricated on a substrate with layers of predetermined weak and strong bond regions where deconstucted layers of devices at or on the weak bond regions. The layers are then peeled and subsequently bonded to produce a multi layer microelectromechanical and microfluidic devices. An arbitrary number of layers can be bonded and stacked to create either microelectromechanical or microfluidic device or a hyrbid type of device. Also disclosed are methods of creating edge interconnects and vias through the substrate to form interconnections between layers and devices thereon.

    Abstract translation: 公开了一种用于制造多层微机电和微流体装置的方法。 多层微机电和微流体装置制造在具有预定的弱和强结合区域的层的衬底上，其中在弱结合区域处或弱结合区上的器件的解构层。 然后将这些层剥离并随后键合以产生多层微机电和微流体装置。 任意数量的层可以被结合和层叠以产生微机电或微流体装置或者高密度类型的装置。 还公开了通过衬底产生边缘互连和通孔以在其上的层和器件之间形成互连的方法。

    INTEGRATED SENSOR AND CIRCUITRY AND PROCESS THEREFOR
    93.
    发明申请
    INTEGRATED SENSOR AND CIRCUITRY AND PROCESS THEREFOR 有权
    集成传感器及其电路及其过程

    公开(公告)号：US20070029629A1

    公开(公告)日：2007-02-08

    申请号：US11458729

    申请日：2006-07-20

    Applicant: Navid Yazdi

    Inventor： Navid Yazdi

    IPC: H01L27/00 ,  G01P15/125 ,  H01L21/465

    CPC classification number: G01P15/18 ,  B81B2201/0235 ,  B81C1/00253 ,  B81C2201/019 ,  G01C19/5719 ,  G01P1/023 ,  G01P15/0802 ,  G01P15/125 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/00014

    Abstract: A micromachined sensor and a process for fabrication and vertical integration of a sensor and circuitry at wafer-level. The process entails processing a first wafer to incompletely define a sensing structure in a first surface thereof, processing a second wafer to define circuitry on a surface thereof, bonding the first and second wafers together, and then etching the first wafer to complete the sensing structure, including the release of a member relative to the second wafer. The first wafer is preferably a silicon-on-insulator (SOI) wafer, and the sensing structure preferably includes a member containing conductive and insulator layers of the SOI wafer. Sets of capacitively coupled elements are preferably formed from a first of the conductive layers to define a symmetric capacitive full-bridge structure.

    Abstract translation: 微机械传感器和晶圆级传感器和电路的制造和垂直集成工艺。 该过程需要处理第一晶片以在其第一表面中不完全地限定感测结构，处理第二晶片以在其表面上限定电路，将第一和第二晶片结合在一起，然后蚀刻第一晶片以完成感测结构 ，包括相对于第二晶片释放元件。 第一晶片优选为绝缘体上硅（SOI）晶片，并且感测结构优选地包括包含SOI晶片的导电层和绝缘体层的构件。 电容耦合元件的组优选地由第一导电层形成以限定对称的电容全桥结构。

    Deflectable microstructure and method of manufacturing the same through bonding of wafers
    94.
    发明授权
    Deflectable microstructure and method of manufacturing the same through bonding of wafers 有权
    可偏转的微结构及其制造方法通过晶片的结合

    公开(公告)号：US07172911B2

    公开(公告)日：2007-02-06

    申请号：US10504714

    申请日：2003-02-14

    Applicant: Edvard Kälvesten ,  Thorbjörn Ebefors ,  Niklas Svedin ,  H{dot over (a)}kan Westin

    Inventor： Edvard Kälvesten ,  Thorbjörn Ebefors ,  Niklas Svedin ,  H{dot over (a)}kan Westin

    IPC: H01L21/00

    CPC classification number: B81C1/0015 ,  B81B2201/042 ,  B81C1/00142 ,  B81C3/002 ,  B81C2201/019 ,  B81C2201/0191 ,  B81C2203/058

    Abstract: A method of making a deflectable, free hanging micro structure having at least one hinge member, the method includes the steps of providing a first sacrificial wafer having a single crystalline material constituting material forming the micro structure. A second semiconductor wafer including necessary components for forming the structure in cooperation with the first wafer is provided. Finite areas of a structured bonding material is provided, on one or both of the wafers at selected locations, the finite areas defining points of connection for joining the wafers. The wafers are bonded using heat and optionally pressure. Sacrificial material is etched away from the sacrificial wafer, patterning the top wafer by lithography is performed to define the desired deflectable microstructures having hinges, and subsequently silicon etch to make the structures.

    Abstract translation: 一种制造具有至少一个铰链构件的可偏转的自由悬挂微结构的方法，所述方法包括以下步骤：提供具有形成微结构的单晶材料构成材料的第一牺牲晶片。 提供了包括与第一晶片协作形成结构的必要部件的第二半导体晶片。 在选定位置的一个或两个晶片上提供结构化接合材料的有限区域，限定用于接合晶片的连接点。 使用热和任选的压力将晶片接合。 牺牲材料被蚀刻离开牺牲晶片，通过光刻来图案化顶部晶片以限定具有铰链的期望的可偏转微结构，并随后进行硅蚀刻以制造结构。

    Vertical integrated circuits
    96.
    发明授权
    Vertical integrated circuits 失效
    垂直集成电路

    公开(公告)号：US07145219B2

    公开(公告)日：2006-12-05

    申请号：US11020753

    申请日：2004-12-23

    Applicant: Sadeg M Faris

    Inventor： Sadeg M Faris

    IPC: H01L29/06

    CPC classification number: B81C1/00238 ,  B81C1/0038 ,  B81C2201/019 ,  G01R31/01 ,  H01L22/20 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/014 ,  Y10S438/977 ,  H01L2924/00

    Abstract: A method for fabricating a vertical integrated circuit is disclosed. Integrated circuits are fabricated on a substrate with layers of predetermined weak and strong bond regions where deconstructed layers of integrated circuits are fabricated at or on the weak bond regions. The layers are then peeled and subsequently bonded to produce a vertical integrated circuit. An arbitrary number of layers can be bonded and stacked in to a separate vertical integrated circuit. Also disclosed are methods of creating edge interconnects and vias through the substrate to form interconnections between layers and devices thereon.

    Abstract translation: 公开了一种用于制造垂直集成电路的方法。 集成电路制造在具有预定的弱结合区域和强结合区域的衬底上，其中集成电路的解构层在弱键区域处或其上制造。 然后将这些层剥离并随后结合以产生垂直集成电路。 任意数量的层可以结合并堆叠到单独的垂直集成电路中。 还公开了通过衬底产生边缘互连和通孔以在其上的层和器件之间形成互连的方法。

    Structures, materials and methods for fabrication of nanostructures
    97.
    发明申请
    Structures, materials and methods for fabrication of nanostructures 审中-公开
    用于制造纳米结构的结构，材料和方法

    公开(公告)号：US20060264014A1

    公开(公告)日：2006-11-23

    申请号：US11335162

    申请日：2006-01-18

    Applicant: Robert Bower

    Inventor： Robert Bower

    IPC: H01L27/12 ,  H01L21/30 ,  H01L21/425

    CPC classification number: B81C99/008 ,  B81C1/00595 ,  B81C2201/014 ,  B81C2201/019

    Abstract: A material having a top portion (active layer) of a thickness and other characteristics optimized for formation of a desired nanostructure, followed by an insulator layer (intermediate or boundary layer) chosen for its electrical insulation and etch resistance from a substrate material formed adjacent to it such that after subsequent processing the substrate may be removed by polishing and etching to leave the nanostructure processed top layer as a thin layer bonded to a 3-d stack or other structure as a thin layer. Thus, the substrate layer has been optimized to have a very high etch rate and to have a large difference in its etch rate and that of the intermediate insulator layer so that it can be selectively etched.

    Abstract translation: 一种具有厚度的顶部（活性层）和为了形成期望的纳米结构而优化的其它特性的材料，其后是绝缘体层（中间层或边界层） 使得在后续处理之后，可以通过抛光和蚀刻去除衬底，以将纳米结构处理的顶层作为薄层结合到作为薄层的3-d叠层或其它结构的薄层。 因此，衬底层已经被优化以具有非常高的蚀刻速率，并且其蚀刻速率和中间绝缘体层的蚀刻速率差异很大，从而可以选择性地蚀刻。

    Method for treating a structure to obtain an internal space and structure having an internal space
    98.
    发明申请
    Method for treating a structure to obtain an internal space and structure having an internal space 有权
    用于处理结构以获得具有内部空间的内部空间和结构的方法

    公开(公告)号：US20060246729A1

    公开(公告)日：2006-11-02

    申请号：US10539638

    申请日：2003-12-04

    Applicant: Michel Bruel

    Inventor： Michel Bruel

    IPC: H01L21/311

    CPC classification number: B81C1/00047 ,  B81C2201/019 ,  C08F210/16 ,  C08F4/65916 ,  C08F210/14 ,  C08F2500/12 ,  C08F2500/04

    Abstract: A method for treating a structure, includes: providing an initial structure having at least one main part and a secondary part which have a contact interface with each other and elements constituting at least one zone to be treated capable of varying in thickness substantially perpendicularly to the interface under the effect of a treatment of its material; and applying the treatment to the zone of the initial structure so as to obtain a final structure such that the variation in the thickness of the zone forms an internal space extending between the parts over at least one zone of the interface and substantially parallel to the interface or within at least one of the parts, spaced apart and substantially parallel to the interface. The invention also concerns the structure with internal space resulting from the displacement of one part relative to another part of the structure.

    Abstract translation: 一种用于处理结构的方法，包括：提供具有至少一个主要部分和次要部分的初始结构，该至少一个主要部分和次要部分彼此具有接触界面，并且构成至少一个待处理区域的元件的厚度基本上垂直于 界面处理其材料的作用; 以及将处理施加到初始结构的区域，以便获得最终结构，使得区域的厚度的变化在界面的至少一个区域之间形成在部件之间延伸的基本平行于界面的内部空间 或者在至少一个部件中，间隔开并且基本上平行于界面。 本发明还涉及由一部分相对于结构的另一部分的位移而产生的内部空间的结构。

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