公开(公告)号：US09653290B2

公开(公告)日：2017-05-16

申请号：US15378015

申请日：2016-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Shih-Fang Hong ,  Chao-Hung Lin ,  Jyh-Shyang Jenq

IPC: H01L21/20 ,  H01L27/12 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L21/02603 ,  H01L21/823807 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

Abstract: A method for manufacturing a nanowire transistor device includes the following steps: A substrate is provided, and the substrate includes a plurality of nanowires suspended thereon. Each of the nanowires includes a first semiconductor core. Next, a first selective epitaxial growth process is performed to form second semiconductor cores respectively surrounding the first semiconductor cores. The second semiconductor cores are spaced apart from the substrate. After forming the second semiconductor core, a gate is formed on the substrate.

公开(公告)号：US20170069543A1

公开(公告)日：2017-03-09

申请号：US14884746

申请日：2015-10-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yu Chang ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Chien-Ting Lin ,  Yi-Ren Chen ,  Shou-Wei Hsieh ,  Hsin-Yu Chen ,  Chun-Hao Lin

IPC: H01L21/8238 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/02129 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有鳍状结构的衬底和围绕鳍状结构的浅沟槽隔离（STI），其中鳍状结构具有顶部和底部; 在STI和顶部上形成第一掺杂层; 并执行第一退火处理。

公开(公告)号：US20170033019A1

公开(公告)日：2017-02-02

申请号：US15294797

申请日：2016-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Hon-Huei Liu ,  Shih-Fang Hong ,  Jyh-Shyang Jenq

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/225

CPC classification number: H01L21/823821 ,  H01L21/2255 ,  H01L21/2256 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/66803 ,  H01L29/7851

Abstract: A semiconductor device includes: a fin-shaped structure on a substrate, in which the fin-shaped structure includes a top portion and a bottom portion; a doped layer around the bottom portion of the fin-shaped structure; a first liner on the doped layer, and a second liner on the top portion and the bottom portion of the fin-shaped structure. Preferably, the first liner and the second liner are made of different material.

Abstract translation: 半导体器件包括：在基板上的鳍状结构，其中鳍状结构包括顶部和底部; 围绕所述鳍状结构的底部的掺杂层; 在掺杂层上的第一衬垫，以及鳍状结构的顶部和底部上的第二衬垫。 优选地，第一衬垫和第二衬套由不同的材料制成。

公开(公告)号：US09530778B1

公开(公告)日：2016-12-27

申请号：US14834439

申请日：2015-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Chih-Kai Hsu ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Chien-Ting Lin ,  Jyh-Shyang Jenq ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/00 ,  H01L27/092 ,  H01L29/51 ,  H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/511 ,  H01L29/517

Abstract: Semiconductor devices having metal gate include a substrate, a first nFET device formed thereon, and a second nFET device formed thereon. The first nFET device includes a first n-metal gate, and the first n-metal gate includes a third bottom barrier metal layer and an n type work function metal layer. The n type work function metal layer directly contacts the third bottom barrier layer. The second nFET device includes a second n-metal gate and the second n-metal gate includes a second bottom barrier metal layer, the n type work function metal layer, and a third p type work function metal layer sandwiched between the second bottom barrier metal layer and the n type work function metal layer. The third p type work function metal layer of the second nFET device and the third bottom barrier metal layer of the first nFET device include a same material.

Abstract translation: 具有金属栅极的半导体器件包括衬底，其上形成的第一nFET器件和形成在其上的第二nFET器件。 第一nFET器件包括第一n型金属栅极，并且第一n型金属栅极包括第三底部阻挡金属层和n型功函数金属层。 n型功函数金属层直接接触第三底层阻挡层。 第二nFET器件包括第二n型金属栅极，第二n型金属栅极包括第二底部阻挡金属层，n型功函数金属层和夹在第二底部阻挡金属之间的第三p型功函数金属层 层和n型功函数金属层。 第二nFET器件的第三p型功函数金属层和第一nFET器件的第三底阻挡金属层包括相同的材料。

公开(公告)号：US20160300942A1

公开(公告)日：2016-10-13

申请号：US14703904

申请日：2015-05-05

Applicant: United Microelectronics Corp.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Jyh-Shyang Jenq

IPC: H01L29/78 ,  H01L21/324 ,  H01L21/02 ,  H01L29/167 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/66803

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first fin-shaped structure thereon; forming a spacer adjacent to the first fin-shaped structure; using the spacer as mask to remove part of the substrate for forming a second fin-shaped structure, in which the second fin-shaped structure comprises a top portion and a bottom portion; and forming a doped portion in the bottom portion of the second fin-shaped structure.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有第一鳍状结构的基底; 形成邻近所述第一鳍状结构的间隔件; 使用间隔件作为掩模来去除用于形成第二鳍状结构的基板的一部分，其中第二鳍状结构包括顶部和底部; 以及在所述第二鳍状结构的底部中形成掺杂部分。

公开(公告)号：US09281209B1

公开(公告)日：2016-03-08

申请号：US14507840

申请日：2014-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Ssu-I Fu ,  Shih-Hung Tsai ,  Yu-Hsiang Hung ,  Jyh-Shyang Jenq

IPC: G03F7/26 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/3081

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a material layer on the substrate; forming a patterned first hard mask on the material layer; forming a patterned second hard mask on the material; utilizing the patterned first hard mask and the patterned second hard mask to remove part of the material layer for forming sacrificial mandrels; forming sidewall spacers adjacent to the sacrificial mandrels; removing the sacrificial mandrels; and using the sidewall spacers to remove part of the substrate.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在所述基板上形成材料层; 在所述材料层上形成图案化的第一硬掩模; 在材料上形成图案化的第二硬掩模; 利用图案化的第一硬掩模和图案化的第二硬掩模去除用于形成牺牲心轴的材料层的一部分; 形成与牺牲心轴相邻的侧壁间隔物; 去除牺牲心轴; 以及使用所述侧壁间隔件来移除所述基板的一部分。

公开(公告)号：US20160064238A1

公开(公告)日：2016-03-03

申请号：US14507840

申请日：2014-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Ssu-I Fu ,  Shih-Hung Tsai ,  Yu-Hsiang Hung ,  Jyh-Shyang Jenq

IPC: H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/3081

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a material layer on the substrate; forming a patterned first hard mask on the material layer; forming a patterned second hard mask on the material; utilizing the patterned first hard mask and the patterned second hard mask to remove part of the material layer for forming sacrificial mandrels; forming sidewall spacers adjacent to the sacrificial mandrels; removing the sacrificial mandrels; and using the sidewall spacers to remove part of the substrate.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在所述基板上形成材料层; 在所述材料层上形成图案化的第一硬掩模; 在材料上形成图案化的第二硬掩模; 利用图案化的第一硬掩模和图案化的第二硬掩模去除用于形成牺牲心轴的材料层的一部分; 形成与牺牲心轴相邻的侧壁间隔物; 去除牺牲心轴; 以及使用所述侧壁间隔件来移除所述基板的一部分。

公开(公告)号：US11271000B2

公开(公告)日：2022-03-08

申请号：US16180010

申请日：2018-11-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Bo-Ruei Cheng ,  Li-Wei Feng

IPC: H01L27/108 ,  H01L29/06 ,  H01L21/762 ,  H01L21/02

Abstract: A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; forming a first oxide layer in the trench; forming a silicon layer on the first oxide layer; performing an oxidation process to transform the silicon layer into a second oxide layer; and planarizing the second oxide layer and the first oxide layer to form a shallow trench isolation (STI).

公开(公告)号：US11121136B2

公开(公告)日：2021-09-14

申请号：US16590387

申请日：2019-10-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng

IPC: H01L27/108 ,  H01L21/311 ,  H01L21/033

Abstract: A method of forming insulating structures in a semiconductor device is provided in the present invention, which includes the steps of forming a first mask layer with mandrels and a peripheral portion surrounding the mandrels, forming spacers on sidewalls of first mask layer, filling up the space between spacers with a second mask layer, removing the spacers to form opening patterns, performing an etch process with the first mask layer and the second mask layer as an etch mask to form trenches in the substrate, and filling up the trenches with an insulating material to form insulating structures.

公开(公告)号：US11049863B2

公开(公告)日：2021-06-29

申请号：US15889182

申请日：2018-02-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Shih-Fang Tzou ,  Chien-Ting Ho ,  Ying-Chiao Wang ,  Yu-Ching Chen ,  Hui-Ling Chuang ,  Kuei-Hsuan Yu

IPC: H01L27/108

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.