公开(公告)号：US20140043920A1

公开(公告)日：2014-02-13

申请号：US13962233

申请日：2013-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Hee SHIN ,  Young Man AHN ,  Seung Mo JUNG ,  You Keun HAN ,  Sang Jhun HWANG

IPC: G01R31/02 ,  G11C7/00

CPC classification number: G01R31/02 ,  G01R31/01 ,  G01R31/26 ,  G01R31/27 ,  G06F13/28 ,  G06F17/5054 ,  G11C5/04 ,  G11C7/1012 ,  G11C7/1021 ,  G11C7/1036 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/406 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/1201 ,  G11C29/14 ,  G11C2029/0401 ,  G11C2029/4002 ,  H03M7/40 ,  H03M13/00

Abstract: A memory device includes a memory cell array and a data input/output circuit. The memory cell array includes a plurality of memory cells connected to a plurality of bit lines and a plurality of word lines. The data input/output circuit is configured to receive data from external data pins of the memory device, output the received data to the memory cell array through a plurality of input/output lines electrically coupled to the plurality of bit lines, receive data read from the memory cell array through the plurality of input/output lines, and output the read data through the external data pins. For each external data pin, the data input/output circuit is configured to output data received at the external data pin to a corresponding input/output line. The corresponding input/output line is selected in response to bit values of a set of bits included in the received data.

Abstract translation: 存储器件包括存储单元阵列和数据输入/输出电路。 存储单元阵列包括连接到多个位线和多个字线的多个存储单元。 数据输入/输出电路被配置为从存储器件的外部数据引脚接收数据，通过电耦合到多个位线的多个输入/输出线将接收到的数据输出到存储单元阵列，从多个位线读取数据 通过多个输入/输出线的存储单元阵列，并通过外部数据引脚输出读取的数据。 对于每个外部数据引脚，数据输入/输出电路被配置为将在外部数据引脚处接收的数据输出到相应的输入/输出线。 响应于包含在接收数据中的一组位的位值来选择相应的输入/输出线。

公开(公告)号：US20130166851A1

公开(公告)日：2013-06-27

申请号：US13336342

申请日：2011-12-23

Applicant: Sandeep ROHILLA

Inventor： Sandeep ROHILLA

IPC: G06F12/00

CPC classification number: G06F13/287 ,  G11C7/10 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1087

Abstract: In managing incoming bus traffic storage for store cell memory (SCM) in a sequential-write, random-read system, a priority encoder system can be used to find a next empty cell in the sequential-write step. Each cell in the SCM has a bit that indicates whether the cell is full or empty. The priority encoder encodes the next empty cell using these bits and the current write pointer. The priority encoder can also find next group of empty cells by being coupled to AND operators that are coupled to each group of cells. Further, a cell locator selector selects a next empty cell location among priority encoders for cell groups of various sizes according to an opcode by appending ‘0’s to cell locations outputs from priority encoders that are smaller than the size of the SCM.

Abstract translation: 在顺序写入随机读取系统中管理存储单元存储器（SCM）的输入总线流量存储器时，优先级编码器系统可用于在顺序写入步骤中找到下一个空单元。 SCM中的每个单元格都有一个位，表示单元格是满还是空。 优先编码器使用这些位和当前写指针对下一个空单元进行编码。 优先编码器还可以通过耦合到耦合到每组单元的AND运算符来找到下一组空单元。 此外，单元定位器选择器根据操作码，通过将小于等于小于SCM大小的优先编码器的单元位置输出相加0来选择各种尺寸的单元组的优先编码器中的下一个空单元位置。

公开(公告)号：US07933156B2

公开(公告)日：2011-04-26

申请号：US12293118

申请日：2006-03-17

Applicant: Klaus W. Ruthemann

Inventor： Klaus W. Ruthemann

IPC: G11C7/10

CPC classification number: G11C7/1036 ,  G11C7/22 ,  G11C7/222 ,  G11C8/06 ,  G11C29/003 ,  G11C29/02

Abstract: An apparatus for adjustment of a digital delay function of a data memory unit comprising said data memory unit (102), an elastic store register, ESR, (104) and read clock and write clock adapted to control read and write operations, a write counter associated with the write clock and a read counter associated with the read clock. Said memory (102) works in series with said ESR (104). The memory (102) delivers two data elements from two logically neighbouring cells. Said ESR (104) writes the two data elements from the memory (102) at every cycle of the write clock, wherein if the write counter is increased by one at a cycle of the write clock the output position in the memory (102) is not changed, and if the write counter is increased by two at one cycle of the write clock the output position in the memory (102) is moved backward by one data element and if the write counter is not changed at one cycle of the write clock the output position in the memory (102) is moved forward by one data element.

Abstract translation: 一种用于调整数据存储单元的数字延迟功能的装置，包括所述数据存储单元（102），弹性存储寄存器ESR（104）和适于控制读写操作的读时钟和写时钟，写计数器 与写入时钟相关联，读取计数器与读取时钟相关联。 所述存储器（102）与所述ESR（104）串联工作。 存储器（102）从两个逻辑上相邻的单元传送两个数据元素。 所述ESR（104）在所述写入时钟的每个周期从所述存储器（102）写入所述两个数据元素，其中如果所述写入计数器在写入时钟的周期增加1，则所述存储器（102）中的输出位置是 如果写入计数器在写入时钟的一个周期增加了两个，则存储器（102）中的输出位置向后移动一个数据元素，并且如果写入计数器在写入时钟的一个周期没有改变 存储器（102）中的输出位置向前移动一个数据元素。

公开(公告)号：US07808844B2

公开(公告)日：2010-10-05

申请号：US11806012

申请日：2007-05-29

Applicant: William Thomas Lynch ,  David James Herbison

Inventor： William Thomas Lynch ,  David James Herbison

IPC: G11C7/00

CPC classification number: G11C29/32 ,  G06F13/1673 ,  G11C7/1036 ,  G11C29/12 ,  G11C29/1201 ,  G11C2029/3202

Abstract: A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.

Abstract translation: 一种存储器访问方案，其采用串联互连的一组或多组移位寄存器，数据可以从其中加载或写入一个或多个存储器件。 也就是说，来自存储器件的数据可以并行加载到移位寄存器组中，然后通过移位寄存器串行移位，直到从移位寄存器组输出并传送到其目的地。 此外，数据可以从/从该组移位寄存器中读取并加载到存储器件中，使得在读取和/或加载数据期间移位寄存器的移位是不间断的。 此外，来自存储器件的数据可以被加载到两个或更多个并行的移位寄存器链中，然后通过移位寄存器链串行移位。

公开(公告)号：US20080158978A1

公开(公告)日：2008-07-03

申请号：US11962216

申请日：2007-12-21

Applicant: Hideki NISHIYAMA

Inventor： Hideki NISHIYAMA

IPC: G11C16/06 ,  G11C7/00

CPC classification number: G11C7/065 ,  G11C7/1036 ,  G11C29/1201 ,  G11C29/40 ,  G11C2029/3202

Abstract: A memory read circuit includes k sense amplifiers provided for respective k bit lines and reading out data from their corresponding bit lines, where k is a natural number, a shift register that includes k flip-flops connected in cascade and arranged to hold outputs from corresponding sense amplifiers, and to output the outputs from the k sense amplifiers as serial data, and expected value setting section arranged to store in the k flip-flops expected value data on the outputs from the corresponding sense amplifiers, and a determination section arranged to determine whether the expected value data stored in the flip-flops matches the outputs from the corresponding sense amplifiers.

Abstract translation: 存储器读取电路包括为各个k位线提供的k个读出放大器，并从其对应的位线读出数据，其中k是自然数，移位寄存器包括级联连接的k个触发器，并被布置为保持相应的输出 感测放大器，并且将来自k个读出放大器的输出作为串行数据输出，以及期望值设置部分，被布置成存储在k个触发器中来自相应的读出放大器的输出的期望值数据;以及确定部， 存储在触发器中的期望值数据是否匹配来自对应读出放大器的输出。

公开(公告)号：US20080094871A1

公开(公告)日：2008-04-24

申请号：US11549178

申请日：2006-10-13

Applicant: WARD PARKINSON

Inventor： WARD PARKINSON

IPC: G11C17/00

CPC classification number: G11C16/26 ,  G11C7/1006 ,  G11C7/1036 ,  G11C7/1075 ,  G11C11/4096 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0076

Abstract: An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh. In some embodiments, the circuitry may further include shift registers and one or more arithmetic logic units to provide a video memory.

Abstract translation: 布置在逻辑列和逻辑行中的非易失性存储器单元的阵列，以及相关联的电路，以使得能够并行地读取或写入行上的一个或多个存储器单元。 在一些实施例中，存储器单元阵列可以包括相变材料。 在一些实施例中，电路可以包括写入驱动器，读取驱动器，读出放大器以及通过扩展刷新来将存储器单元与读出放大器隔离的电路。 在一些实施例中，电路还可以包括移位寄存器和一个或多个算术逻辑单元以提供视频存储器。

公开(公告)号：US20060067129A1

公开(公告)日：2006-03-30

申请号：US11212480

申请日：2005-08-25

Applicant: Francesco La Rosa ,  Thierry Giovinazzi

Inventor： Francesco La Rosa ,  Thierry Giovinazzi

IPC: G11C16/06

CPC classification number: G11C7/12 ,  G11C7/1036

Abstract: The present invention relates to a method for reading memory cells by means of sense amplifiers, the memory cells being linked to bit lines, the reading of each memory cell comprising a phase of precharging the bit line to which the memory cell is linked and a phase of actually reading the memory cell. According to the present invention, each sense amplifier is used to precharge at least two bit lines, then to read one memory cell in one of the precharged bit lines. The present invention applies particularly to serial memories, for the precharge-ahead of bit lines having the same partial address, while a read address is being received.

公开(公告)号：US06914828B2

公开(公告)日：2005-07-05

申请号：US10440188

申请日：2003-05-19

Applicant: Takashi Kono

Inventor： Takashi Kono

IPC: G11C11/407 ,  G11C7/10 ,  G11C11/34 ,  G11C11/40 ,  G11C11/408 ,  G11C11/409 ,  G11C19/00 ,  H01L27/148

CPC classification number: G11C7/1051 ,  G11C7/103 ,  G11C7/1036 ,  G11C19/00 ,  G11C2207/107

Abstract: An amplifier circuit (R/A) conducts the first stage of ordering of whether to output data of four data bus pairs at the first half (first or second) or at the last half (third or fourth) based on the value of a signal EZORG1 reflecting the value of the least significant second bit of an externally applied column address. A switch circuit conducts the second stage of ordering to determine which is to be the first and the second of the two data output as the first half and to determine which is to be the third and the fourth of the two data output as the last half based on the value of a signal EZORG0 reflecting the value of the least significant bit in the externally applied column address.

Abstract translation: 放大器电路（R / A）根据信号的值进行在前半（第一或第二）或后半（第三或第四）输出四个数据总线对的数据的排序的第一阶段 EZORG 1反映外部应用列地址的最低有效第二位的值。 开关电路进行第二阶段的排序，以确定作为上半部分输出的两个数据中的第一个和第二个是哪一个，并确定哪个是作为后半部分的两个数据输出中的第三个和第四个 基于反映外部施加的列地址中的最低有效位的值的信号EZORG 0的值。

公开(公告)号：US06910096B2

公开(公告)日：2005-06-21

申请号：US10452339

申请日：2003-06-02

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C7/10 ,  G11C8/02 ,  H04B7/185 ,  G11C8/00 ,  G06F12/02

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US06801144B2

公开(公告)日：2004-10-05

申请号：US10678742

申请日：2003-10-02

Applicant: Katsuki Matsudera ,  Masaru Koyanagi ,  Kazuhide Yoneya ,  Toshiki Hisada

Inventor： Katsuki Matsudera ,  Masaru Koyanagi ,  Kazuhide Yoneya ,  Toshiki Hisada

IPC: H03M900

CPC classification number: G11C7/1036

Abstract: An input/output circuit inputs/outputs serial data. A register section comprises a first and a second register. The first register converts the serial data into parallel data. The second register converts parallel data into serial data. A first control signals supply a conversion timing for each bit when the serial data are converted into the parallel data. A second control signals supply a conversion timing for each bit when the parallel data are converted into the serial data. The signal generating circuit controls a timing of rise or fall of the first control signals and sets which of the memory cells should store a value for each bit, of the serial data, and controls a timing of rise or fall of the second control signals and sets which number of value of the serial data should be the value for each bit, of the parallel data read from the memory cells.

Abstract translation: 输入/输出电路输入/输出串行数据。 寄存器部分包括第一和第二寄存器。 第一个寄存器将串行数据转换为并行数据。 第二个寄存器将并行数据转换为串行数据。 当串行数据被转换成并行数据时，第一控制信号为每个位提供转换定时。 当并行数据被转换成串行数据时，第二控制信号为每个位提供转换定时。 信号发生电路控制第一控制信号的上升或下降的定时，并设置哪个存储单元应存储串行数据的每个位的值，并且控制第二控制信号的上升或下降的定时，以及 将串行数据的值的数量设置为从存储器单元读取的并行数据的每个位的值。