公开(公告)号：US09813061B1

公开(公告)日：2017-11-07

申请号：US15150869

申请日：2016-05-10

Applicant: Altera Corporation

Inventor： Herman Henry Schmit ,  David Lewis

IPC: H03K19/003 ,  G06F7/501 ,  H03K19/23 ,  H03K19/007 ,  G06F11/20

CPC classification number: H03K19/00392 ,  G06F7/501 ,  G06F11/187 ,  G06F11/2089 ,  G06F11/2094 ,  H03K19/00369 ,  H03K19/0075 ,  H03K19/23

Abstract: Integrated circuits such as application specific integrated circuits or programmable logic devices may include multiple copies of a same circuit together with a majority vote circuit in a configuration that is sometimes also referred to as multi-mode redundancy. An adder circuit may be coupled to these multiple copies and produce a carry-out signal and a sum signal based on signals received from the multiple copies. The carry-out signal of the adder circuit may provide the result of the majority vote operation. A logic exclusive OR gate may perform a logic exclusive OR operation between the sum signal and the carry-out signal, thereby generating an error signal. The error signal may indicate that one of the multiple copies produces an output that is different than the outputs produced by the other copies.

公开(公告)号：US09812216B1

公开(公告)日：2017-11-07

申请号：US15197442

申请日：2016-06-29

Applicant: Altera Corporation

Inventor： Kalyana Kantipudi

IPC: G01R31/3173 ,  G11C19/00 ,  G01R31/317

CPC classification number: G11C19/00 ,  G01R31/31704 ,  G01R31/31727 ,  G01R31/3173 ,  G11C29/08 ,  G11C2029/0401 ,  G11C2029/0409

Abstract: A shift register circuit generates a clock enable signal in response to a start signal and in response to a clock signal. The shift register circuit generates multiple pulses in the clock enable signal in response to a single transition in the start signal and in response to control signals having values that indicate to generate more than one pulse in the clock enable signal. A multiplexer circuit provides an output signal for testing an electronic circuit based on an input signal or based on the clock signal in response to the clock enable signal.

公开(公告)号：US20170310340A1

公开(公告)日：2017-10-26

申请号：US15649444

申请日：2017-07-13

Applicant: Altera Corporation

Inventor： Jeffrey Schulz

IPC: H03M13/09

CPC classification number: H04L1/0078 ,  H03M13/09 ,  H04L1/1607 ,  H04L1/1829

Abstract: A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet formation logic that creates packets that include empty fields for sequence number information, acknowledgement information, and cyclic redundancy check information. The hardwired circuitry of the memory interface may be used to insert a sequence number, an acknowledgement, and cyclic redundancy check information into the empty fields.

公开(公告)号：US09793893B1

公开(公告)日：2017-10-17

申请号：US15483796

申请日：2017-04-10

Applicant: Altera Corporation

Inventor： Hoong Chin Ng

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/00

CPC classification number: H03K19/0005 ,  H03K19/01825 ,  H03K19/018564 ,  H03K19/17744

Abstract: A termination circuit includes a first transistor coupled to a first pad, a first resistor coupled between the first transistor and a second pad, and an operational amplifier circuit. The termination circuit provides termination impedance to input signals received at the first and second pads. The first transistor generates a first common mode voltage of the input signals at a first node between the first resistor and the first transistor in response to an output signal of the operational amplifier circuit. The operational amplifier circuit generates the output signal based on the first common mode voltage of the input signals and based on a second common mode voltage of the input signals. The termination circuit generates the second common mode voltage at a second node that is a different node than the first node.

公开(公告)号：US20170287872A1

公开(公告)日：2017-10-05

申请号：US15087907

申请日：2016-03-31

Applicant: Altera Corporation

Inventor： Minghao Shen

IPC: H01L25/065 ,  H01L23/495 ,  H01L21/56 ,  H01L23/14 ,  H01L23/31 ,  H01L21/48 ,  H01L25/00 ,  H01L23/367

CPC classification number: H01L25/0655 ,  H01L21/4839 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/565 ,  H01L21/568 ,  H01L23/13 ,  H01L23/142 ,  H01L23/145 ,  H01L23/3157 ,  H01L23/367 ,  H01L23/49506 ,  H01L23/49562 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/73267 ,  H01L2924/15192 ,  H01L2924/18162

Abstract: An integrated circuit package may include a first conductive pad on an interposer substrate, and a second conductive pad formed on a front surface of an integrated circuit die. The second conductive pad may directly contact the first conductive pad on the interposer substrate. The integrated circuit package may further include a package substrate having a cavity, in which the interposer substrate and the integrated circuit are disposed in the cavity. The interposer substrate may include interconnect pathways that are electrically coupled to the first and second conductive pads. A heat spreader may subsequently form over the integrated circuit die and the package substrate.

公开(公告)号：US09780793B2

公开(公告)日：2017-10-03

申请号：US14989549

申请日：2016-01-06

Applicant: ALTERA CORPORATION

Inventor： Christopher Sun Young Chen

IPC: H03K19/177 ,  H03K19/0185

CPC classification number: H03K19/1774 ,  H03K19/018585 ,  H03K19/17736 ,  H03K19/1776

Abstract: Transistors degrade when subjected to voltage stress. Methods are described for reducing this aging problem by applying a reverse voltage to the gates of the circuit on an intermittent or periodic basis. By applying such a voltage for a brief period of time such as one second, the aging process is essentially nullified.

公开(公告)号：US09774478B1

公开(公告)日：2017-09-26

申请号：US14676583

申请日：2015-04-01

Applicant: ALTERA CORPORATION

Inventor： David W. Mendel ,  Han Hua Leong

IPC: H04L25/14 ,  H04L12/24 ,  H04L12/875 ,  H04L12/26

CPC classification number: H04L25/14 ,  G06F5/06 ,  H04L41/0896 ,  H04L43/087 ,  H04L47/56

Abstract: Circuits and methods are disclosed for low-skew bonding of a plurality of data channels into a multi-lane data channel. In one embodiment, phase-measuring first-in first-out buffer circuits buffer pre-buffer parallel data signals and generate phase-measurement signals. A channel-bonding control circuit receives the phase-measurement signals and generates bit-slip control signals. Transmission bit-slip circuits slip integer numbers of bits based on the bit-slip control signals. Bypass registers may be used when the integer number of bits is greater or equal to the parallel width of a lane. In another embodiment, the channel-bonding control circuit receives the phase-measurement signals from the phase-measuring FIFO buffer circuits and generates clock-slip control signals. Clock slip circuits controllably slip parallel clock signals by integer numbers of unit intervals of a serial clock signal. Various other aspects, features, and embodiments are also disclosed.

公开(公告)号：US09772649B1

公开(公告)日：2017-09-26

申请号：US14724166

申请日：2015-05-28

Applicant: ALTERA CORPORATION

Inventor： David W. Mendel

IPC: G06F1/10 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F1/10 ,  G06F13/161 ,  G06F13/4022 ,  G06F13/4072

Abstract: In accordance with an embodiment of the invention, higher-speed outgoing data paths are used to transmit oversampled data signals, and corresponding slower-speed return data paths are used to receive return data signals. A channel-bonding control circuit measures the skew between the returned data signals and generates bit-slip and/or word-slip control signals to compensate for the skew. Transmission bit-slip (or, alternatively, clock-slip) circuits slip integer numbers of bits based on the bit-slip control signals. Bypass registers (or, alternatively, FIFO write or read enable signals) may be used to slip a whole word when the integer number of bits to slip is greater or equal to the parallel width of a lane. Various other aspects, features, and embodiments are also disclosed.

公开(公告)号：US20170270995A1

公开(公告)日：2017-09-21

申请号：US15614221

申请日：2017-06-05

Applicant: Altera Corporation

Inventor： Krzysztof Maryan ,  Gordon Raymond Chiu ,  Warren Nordyke ,  Navid Azizi

IPC: G11C11/4076 ,  G06F1/12 ,  G11C11/4093 ,  G11C7/10 ,  G11C8/18 ,  G11C29/02

CPC classification number: G11C11/4076 ,  G06F1/12 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/18 ,  G11C11/4093 ,  G11C29/023

Abstract: In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer. The method includes, after a period when the values of both the first and second components are at a first logic state, but before receiving a burst of clock edges in the differential strobe signal, detecting a transition in the first component from the first logic state to a second logic state, and in response to the detected transition, asserting an enable signal. The method further includes receiving, by a gating logic block, the enable signal and the output of the first buffer, and, when the enable signal is asserted, un-gating the output of the first buffer.

公开(公告)号：US09767321B1

公开(公告)日：2017-09-19

申请号：US14249970

申请日：2014-04-10

Applicant: Altera Corporation

Inventor： Bruce B. Pedersen

IPC: H03K19/00 ,  G06F21/76

CPC classification number: G06F21/76 ,  G06F21/57 ,  G06F21/74 ,  H03K19/17768

Abstract: Systems and methods are disclosed for allowing security features to be selectively enabled during device configuration. For example, a programmable integrated circuit device is provided that receives configuration data and security requirement data. Control circuitry compares enabled security features in the device against the security requirements, and can configure the programmable integrated circuit device with the configuration data or prevent such configuration. Control circuitry may also use the security requirement data to set security features within the device.