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    Speculative circuit design component graphical user interface
    4.
    发明授权
    Speculative circuit design component graphical user interface 有权

    公开(公告)号：US10157250B1

    公开(公告)日：2018-12-18

    申请号：US15390076

    申请日：2016-12-23

    Applicant: Altera Corporation

    Inventor： Benjamin Michael Joshua Gamsa ,  Gordon Raymond Chiu

    IPC: G06F17/50

    Abstract: In one embodiment, a tangible, non-transitory, computer-readable medium, includes instructions to receive a first circuit design, determine one or more variations of the first circuit design using register retiming with speculative circuit design changes, determine one or more performance improvements of the variations when fed clock signals over the first circuit design, determine one or more tradeoffs of the one or more variations of the first circuit design in comparison to the first circuit design, display a summary of the one or more variations of the first circuit design, the one or more performance improvements, and the one or more tradeoffs, and provide a user-selectable user interface element to enable selection of the first circuit design, at least one of the one or more variations of the first circuit design, or a combination thereof.

    Register retiming and verification of an integrated circuit design
    7.
    发明授权
    Register retiming and verification of an integrated circuit design 有权
    注册集成电路设计的重新定时和验证

    公开(公告)号：US09529947B1

    公开(公告)日：2016-12-27

    申请号：US14525948

    申请日：2014-10-28

    Applicant: Altera Corporation

    Inventor： Gordon Raymond Chiu

    IPC: G06F17/50

    CPC classification number: G06F17/5031 ,  G06F17/5018 ,  G06F17/5081 ,  G06F2217/62 ,  G06F2217/84

    Abstract: A circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the circuit design description, whereby registers are moved across combinational gates, information about the register moves are recorded, and ultimately a modified circuit design description is created. The circuit design computing equipment may perform sequential equivalence checking to ensure that the circuit design description and the modified circuit design description are sequentially equivalent. To facilitate the sequential equivalence checking, the circuit design computing equipment may augment the two circuit design descriptions based on the information recorded during register retiming.

    Abstract translation: 电路设计描述可以具有寄存器和组合门。 电路设计计算设备可以对电路设计描述执行寄存器重新定时，由此寄存器在组合门上移动，记录关于寄存器移动的信息，最终创建修改的电路设计描述。 电路设计计算设备可以执行顺序等效性检查，以确保电路设计描述和修改的电路设计描述是顺序相等的。 为了便于顺序等同性检查，电路设计计算设备可以基于在寄存器重新定时期间记录的信息来增加两个电路设计描述。

    METHODS AND APPARATUS FOR PROBING SIGNALS FROM A CIRCUIT AFTER REGISTER RETIMING
    8.
    发明申请
    METHODS AND APPARATUS FOR PROBING SIGNALS FROM A CIRCUIT AFTER REGISTER RETIMING 有权
    用于从注册表返回后的电路中检测信号的方法和装置

    公开(公告)号：US20160350468A1

    公开(公告)日：2016-12-01

    申请号：US14726237

    申请日：2015-05-29

    Applicant: Altera Corporation

    Inventor： Gordon Raymond Chiu

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/5054 ,  G06F17/5077 ,  G06F2217/14 ,  G06F2217/84

    Abstract: A circuit design may have registers and combinational gates. Circuit design computing equipment may perform register retiming in the circuit design, whereby registers are moved across combinational gates. Information about the register moves may be recorded, and a modified circuit design is created. The circuit design computing equipment may implement the circuit design in an integrated circuit. A logic analyzer may be used to debug the circuit design implemented in the integrated circuit in real-time and at high-speed. To facilitate the debugging process, the circuit design computing equipment may augment the integrated circuit and/or compensate for register retiming based on the information recorded during register retiming.

    Abstract translation: 电路设计可以具有寄存器和组合门。 电路设计计算设备可以在电路设计中执行寄存器重新定时，由此寄存器在组合门上移动。 可以记录关于寄存器移动的信息，并且创建修改的电路设计。 电路设计计算设备可以在集成电路中实现电路设计。 可以使用逻辑分析器来实时和高速地对集成电路中实现的电路设计进行调试。 为了便于调试过程，电路设计计算设备可以基于在寄存器重新定时期间记录的信息来增加集成电路和/或补偿寄存器重新定时。

    Memory interface circuitry with data strobe signal sharing capabilities
    9.
    发明授权
    Memory interface circuitry with data strobe signal sharing capabilities 有权
    具有数据选通信号共享功能的存储器接口电路

    公开(公告)号：US08897083B1

    公开(公告)日：2014-11-25

    申请号：US13715484

    申请日：2012-12-14

    Applicant: Altera Corporation

    Inventor： Navid Azizi ,  Gordon Raymond Chiu

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/1066

    Abstract: An integrated circuit may include memory interface circuitry for communicating with off-chip memory. The memory interface circuitry may receive data signals and data strobe signals from different memory devices via respective data ports and data strobe ports. The memory interface circuitry may be operable in at least first and second modes. In the first mode, data signals from each memory device may be received at two respective data ports while the data strobe signal from one memory device is used to clock the data signals at two corresponding read capture registers. In the second mode, data signals from first and second memory devices may be received via first and second data ports, respectively. The data strobe signal from the first memory device may be ignored while the data strobe signal from the second memory device is used to clock the data signals at two corresponding read capture registers.

    Abstract translation: 集成电路可以包括用于与片外存储器通信的存储器接口电路。 存储器接口电路可以经由相应的数据端口和数据选通端口从不同的存储器件接收数据信号和数据选通信号。 存储器接口电路可以在至少第一和第二模式中操作。 在第一模式中，来自每个存储器件的数据信号可以在两个相应的数据端口处被接收，而来自一个存储器件的数据选通信号用于在两个对应的读取捕获寄存器上对数据信号进行时钟。 在第二模式中，可以分别经由第一和第二数据端口接收来自第一和第二存储器设备的数据信号。 可以忽略来自第一存储器件的数据选通信号，而来自第二存储器件的数据选通信号用于在两个对应的读取捕获寄存器上对数据信号进行时钟。

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