公开(公告)号：US20050162187A1

公开(公告)日：2005-07-28

申请号：US11025774

申请日：2004-12-29

Applicant: Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

Inventor： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

IPC: C07K14/47 ,  C07K16/28 ,  H03K19/177

CPC classification number: C07K16/28 ,  A61K2039/505 ,  C07K14/47

Abstract: A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed I/O modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.

Abstract translation: 用于逻辑阵列的I / O端子的可编程I / O元件适用于根据双速数据速率和零总线周转等高速I / O模式进行工作。 I / O元件可以包括具有两个寄存器的输入块，用于在备用时钟边缘上从终端注册输入信号。 另外或替代地，它可以包括具有两个寄存器的输出块，该两个寄存器在相同的时钟沿上单独地寄存来自阵列的输出信号，以及交替地输出这些信号的多路复用器。 对于双向端子，多路复用器输出可通过输出缓冲器连接到I / O端子，并且输出使能块为输出缓冲器的选通输入提供使能信号。 可编程延迟可以包括在输入，输出和输出使能路径中，特别是提供比输出缓冲器的关断时间更慢的导通时间。

公开(公告)号：US06919231B1

公开(公告)日：2005-07-19

申请号：US10809560

申请日：2004-03-24

Applicant: Shriram Ramanathan ,  Chin Chang Cheng ,  Alan M. Myers

Inventor： Shriram Ramanathan ,  Chin Chang Cheng ,  Alan M. Myers

IPC: H01L21/48 ,  H01L21/68 ,  H01L23/473 ,  H01L23/34

CPC classification number: H01L23/473 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/16195

Abstract: A method of forming channels on a die or other substrate. Also disclosed are liquid cooling systems including such channels.

公开(公告)号：US06906501B2

公开(公告)日：2005-06-14

申请号：US10434207

申请日：2003-05-09

Applicant: Chin-Chang Wu ,  Hurng-Liang Chou ,  Nan-Ying Shen ,  Yao-Jen Chang

Inventor： Chin-Chang Wu ,  Hurng-Liang Chou ,  Nan-Ying Shen ,  Yao-Jen Chang

IPC: H02M3/158 ,  G05F1/40

CPC classification number: H02M3/1584

Abstract: A control method for the parallel-connected power converters includes a control circuit comprising a voltage feedback circuit and a current feed-forward circuit. The voltage feedback circuit, consisting of a voltage regulated control circuit and a waveform control circuit, is used to control the power converter's output voltage with constant amplitude and low total harmonic distortion. By adjusting the gain of waveform control circuit, it can regulate the current distribution among the parallel-connected power converters. The current feed-forward circuit separates the power converter's output current into the fundamental component and the harmonic component, and amplifies them by different gain. The amplified fundamental component acts as a fundamental resistor to suppress the circulating current among the parallel-connected power converters, and the amplified harmonic component acts as a harmonic damper for preventing from high frequency oscillation generated by the L-C filter.

Abstract translation: 并联电力转换器的控制方法包括：电压反馈电路和电流前馈电路的控制电路。 电压反馈电路由电压调节控制电路和波形控制电路组成，用于以恒定幅度和低总谐波失真来控制功率转换器的输出电压。 通过调整波形控制电路的增益，可以调节并联电源转换器之间的电流分布。 电流前馈电路将功率转换器的输出电流分为基波分量和谐波分量，并通过不同的增益进行放大。 放大的基波分量作为基波电阻来抑制并联功率转换器中的循环电流，并且放大的谐波分量作为用于防止由L-C滤波器产生的高频振荡的谐波阻尼器。

公开(公告)号：US06870413B1

公开(公告)日：2005-03-22

申请号：US10017933

申请日：2001-12-14

Applicant: Tzung-Chin Chang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Yan Chong ,  Xiaobao Wang ,  Philip Pan ,  Gopinath Rangan ,  In Whan Kim

Inventor： Tzung-Chin Chang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Yan Chong ,  Xiaobao Wang ,  Philip Pan ,  Gopinath Rangan ,  In Whan Kim

IPC: H03K3/3565 ,  H03K3/012

CPC classification number: H03K3/3565

Abstract: A Schmitt trigger circuit has an adjustable hysteresis characteristic by providing a plurality of feedback circuits that differently affect at least one, and preferably both, of the circuit's upper trip point level and lower trip point level. The upper trip point level can be adjusted by selecting a desired feedback circuit from a first set of feedback circuits, and/or the lower trip point level can be adjusted by selecting a desired feedback circuit from a second set of feedback circuits. Feedback circuit selection is achieved by one or more control signals that may be programmable. The hysteresis characteristic can be adjusted to meet desired noise margin, delay, and input recognition criteria at different VCC levels. The Schmitt trigger circuit may be a CMOS Schmitt trigger with two input stage NMOS, two input stage PMOS transistors, a first set of NMOS feedback circuits, and a second set of PMOS feedback circuits.

Abstract translation: 施密特触发电路具有可调滞后特性，通过提供多个反馈电路，其不同地影响电路的上跳点电平和较低跳变点电平的至少一个，优选两者。 可以通过从第一组反馈电路中选择所需的反馈电路来调整上跳点电平，和/或可以通过从第二组反馈电路中选择所需的反馈电路来调整下跳变点电平。 反馈电路选择由一个或多个可编程的控制信号来实现。 可以调节滞后特性，以满足不同VCC电平下的所需噪声容限，延迟和输入识别准则。 施密特触发电路可以是具有两个输入级NMOS，两个输入级PMOS晶体管，第一组NMOS反馈电路组和第二组PMOS反馈电路的CMOS施密特触发器。

公开(公告)号：US20050053515A1

公开(公告)日：2005-03-10

申请号：US10660354

申请日：2003-09-10

Applicant: Stephen Yates ,  Felipe Fuentes ,  Peter Michalakos ,  Chin Chang ,  Brian Krafthefer ,  Mark Kaiser

Inventor： Stephen Yates ,  Felipe Fuentes ,  Peter Michalakos ,  Chin Chang ,  Brian Krafthefer ,  Mark Kaiser

IPC: A61L9/16 ,  A61L9/20 ,  B01D53/04 ,  B01D53/86 ,  B64D13/00

CPC classification number: B01D53/8668 ,  A61L9/16 ,  A61L9/20 ,  B01D53/04 ,  B01D53/0446 ,  B01D2253/102 ,  B01D2253/308 ,  B01D2255/802 ,  B01D2257/708 ,  B01D2259/41 ,  B01D2259/4508 ,  B01D2259/4575 ,  B64D13/00 ,  B64D2013/0651 ,  F24F2003/1628

Abstract: An air quality system comprising at least one air cleaner unit in communication with an interior air space. In one embodiment, an air quality system for an aircraft comprises a first set of air cleaner units in communication with a lower plenum of the aircraft recirculation system and a second set of air cleaner units in communication with an upper plenum of the aircraft recirculation system. Each air cleaner unit comprises at least one adsorbent unit in combination with at least one photocatalytic oxidation unit. In one embodiment, an air cleaner unit comprises a relatively weak adsorbent material upstream from a photocatalytic oxidation unit, and a relatively strong adsorbent material downstream from the photocatalytic oxidation unit. Methods for removing a pollutant from an air stream and for making an air cleaner unit are also disclosed.

Abstract translation: 空气质量系统，包括与内部空气空间连通的至少一个空气净化器单元。 在一个实施例中，用于飞行器的空气质量系统包括与飞机再循环系统的下部通风室连通的第一组空气净化器单元和与飞行器再循环系统的上部空间连通的第二组空气净化器单元。 每个空气净化器单元包括与至少一个光催化氧化单元组合的至少一个吸附单元。 在一个实施方案中，空气净化器单元包括来自光催化氧化单元上游的相对较弱的吸附材料和在光催化氧化单元下游的较强吸附材料。 还公开了从空气流中除去污染物和制造空气净化器单元的方法。

公开(公告)号：US06834518B1

公开(公告)日：2004-12-28

申请号：US10721261

申请日：2003-11-26

Applicant: Chin-Chang Shih ,  Chin-Tien Huang

Inventor： Chin-Chang Shih ,  Chin-Tien Huang

IPC: D04B2120

CPC classification number: D04B21/08 ,  D10B2503/02

Abstract: A knitting process for a fabric curtain integrated with a trimming, is constructed in a given length using a knitting machine with preset numbers of warp and weft characterized by having the cable stitch pattern below a section of fabric in a given length to facilitate the knitting process to give better quality and additional value to the merchandise.

Abstract translation: 使用具有预定数量的经纬纱的针织机以给定的长度构造用于修整的织物帘布的编织工艺，其特征在于在给定长度的织物部分下方具有电缆针迹图案，以便于编织过程 为商品提供更好的品质和附加价值。

公开(公告)号：USD496751S1

公开(公告)日：2004-09-28

申请号：US29186478

申请日：2003-07-15

Applicant: Chin-Chang Lin

Designer： Chin-Chang Lin

公开(公告)号：US06768047B2

公开(公告)日：2004-07-27

申请号：US10170906

申请日：2002-06-13

Applicant: Chin Chang ,  Gert W. Bruning

Inventor： Chin Chang ,  Gert W. Bruning

IPC: H01L31042

CPC classification number: H05B33/0815 ,  H02J7/35 ,  H02M3/1582 ,  H05B33/0803 ,  H05B33/0818 ,  H05B37/00 ,  Y10S136/291 ,  Y10S136/293 ,  Y10S323/906 ,  Y10S362/80

Abstract: An autonomous solid state lighting system has a charge mode which collects energy and produces electric power with a solid state energy source, converts the voltage of the electric power using a bi-directional power converter, and stores the power in an energy storage device. A discharge mode draws electric power from the energy storage device, converts the voltage of the electric power using the bi-directional power converter, and produces light from a solid state light source. A controller controls the charge and discharge modes. In one embodiment, the solid state energy source can be a solar cell panel, the solid state light source can be an LED module, and the energy storage device can be a battery pack.

Abstract translation: 自主固态照明系统具有收集能量并利用固态能源产生电力的充电模式，使用双向电力转换器转换电力的电压，并将电力存储在能量存储装置中。 放电模式从能量存储装置抽取电力，使用双向电力转换器转换电力的电压，并从固态光源产生光。 控制器控制充电和放电模式。 在一个实施例中，固态能源可以是太阳能电池板，固态光源可以是LED模块，并且能量存储装置可以是电池组。

公开(公告)号：US06749476B2

公开(公告)日：2004-06-15

申请号：US09986175

申请日：2001-11-07

Applicant: Chih-Chin Chang

Inventor： Chih-Chin Chang

IPC: H01J924

CPC classification number: H01J29/92 ,  H01J31/127 ,  H01J2329/90 ,  H01J2329/92

Abstract: an FED cathode plate with internal via includes an internal via; a second dielectric layer; a second gate line; a metal layer 12 covering the gate line and the internal via; and a contact. The internal via is located on a typical tape line. The second dielectric layer is located on the tape line and abutted against the internal via, thereby connecting to an anode by an adhesive. The second gate line is located on the second dielectric layer and abutted against the internal via. The metal layer is covered over the first gate line, the internal via, and the second gate line; and the contact is located on the tape line and connected adjacent to the second dielectric layer, thereby electrically connecting a lead to outside.

Abstract translation: 具有内部通孔的FED阴极板包括内部通孔; 第二电介质层; 第二条门线; 覆盖栅极线和内部通孔的金属层12; 和联系人。 内部通孔位于典型的磁带线上。 第二电介质层位于带状线上并抵靠内部通孔，从而通过粘合剂连接到阳极。 第二栅极线位于第二电介质层上并抵靠内部通孔。 金属层被覆盖在第一栅极线，内部通孔和第二栅极线上; 并且触点位于带状线上并且与第二电介质层相邻地连接，从而将引线电连接到外部。

公开(公告)号：US06733679B2

公开(公告)日：2004-05-11

申请号：US10005737

申请日：2001-11-06

Applicant: Valery M. Dubin ,  Chin-Chang Cheng ,  Christopher D. Thomas

Inventor： Valery M. Dubin ,  Chin-Chang Cheng ,  Christopher D. Thomas

IPC: C02F158

CPC classification number: C02F1/4672 ,  C02F1/52 ,  C02F1/66 ,  C02F1/72 ,  C02F2101/20 ,  C02F2103/16 ,  C02F2209/02 ,  C02F2209/06 ,  Y10S204/13

Abstract: A method of treating an electroless plating waste is provided. The waste is contained and an ability of a reducing agent to reduce a metal of the waste is decreased, for example by adding a stabilizing chemical or by exposing the waste to an anode to which a positive voltage is applied. Poisonous and explosive gases evolve from the waste, which are vented. Upon completion, the waste is drained.

Abstract translation: 提供了一种处理无电镀废料的方法。 废弃物被包含，并且还原剂减少废物金属的能力降低，例如通过添加稳定化学品或通过将废物暴露于施加正电压的阳极。 有毒和爆炸性气体从排放的废物中排出。 完成后，废物被排干。