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    System, apparatus and method for performing antenna diversity selection based on multi-symbol correlations
    111.
    发明授权
    System, apparatus and method for performing antenna diversity selection based on multi-symbol correlations 有权

    公开(公告)号：US10911129B1

    公开(公告)日：2021-02-02

    申请号：US16711824

    申请日：2019-12-12

    Applicant: Silicon Laboratories Inc.

    Inventor： Hendricus De Ruijter ,  Antonio Torrini ,  Yan Zhou ,  David Trager

    IPC: H04B7/10 ,  H04B7/08 ,  H04B17/318

    Abstract: In one embodiment, an apparatus includes: an antenna switch to receive a first radio frequency (RF) signal from a first antenna and a second RF signal from a second antenna and controllable to output a selected one of the first and second RF signals; an RF circuit to receive and process the first and second RF signals; at least one mixer to downconvert the first and second RF signals to first and second baseband signals; and an antenna diversity control circuit to receive sub-symbol portions of a first plurality of symbols of the first baseband signal and sub-symbol portions of a second plurality of symbols of the second baseband signal, and control the antenna switch to output one of the first and second RF signals, based at least in part on one or more of the sub-symbol portions of the first and second pluralities of symbols.

    Integrated circuit clock management during low power operations
    112.
    发明授权
    Integrated circuit clock management during low power operations 有权

    公开(公告)号：US10903838B1

    公开(公告)日：2021-01-26

    申请号：US16656867

    申请日：2019-10-18

    Applicant: Silicon Laboratories Inc.

    Inventor： Brian Taylor Brunn ,  Paul Ivan Zavalney ,  Adrianus Josephus Bink ,  Chester Yu

    IPC: G06F1/08 ,  G06F1/324 ,  H03K19/00

    Abstract: An integrated circuit includes a clock management unit that selectively provides a clock signal, an energy management circuit that provides an internal power supply voltage to an internal voltage rail in response to an external power supply voltage, and has a capacitor coupled between the internal voltage rail and a reference voltage terminal, and a clocked digital circuit that is coupled to the internal voltage rail and the reference voltage terminal and operates in synchronism with the clock signal. The clock management unit provides the clock signal at a first frequency during a standby state, continuously at a second frequency higher than the first frequency during an active state, and during a first clock cycle following an end of the standby state while suppressing the clock signal during at least one subsequent clock cycle during a transition state between the standby state and the active state.

    Digital oversampling clock and data recovery circuit
    114.
    发明授权
    Digital oversampling clock and data recovery circuit 有权

    公开(公告)号：US10826677B2

    公开(公告)日：2020-11-03

    申请号：US16546691

    申请日：2019-08-21

    Applicant: Silicon Laboratories Inc.

    Inventor： Hua Beng Chan ,  Rex Wong Tak Ying ,  Ricky Setiawan ,  Obaida Mohammed Khaled Abu Hilal

    IPC: H04L7/033

    Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

    Ultra-Low Power Mesh Network
    117.
    发明申请
    Ultra-Low Power Mesh Network 审中-公开

    公开(公告)号：US20200336319A1

    公开(公告)日：2020-10-22

    申请号：US16918342

    申请日：2020-07-01

    Applicant: Silicon Laboratories Inc.

    Inventor： Partha Sarathy MURALI ,  Ajay MANTHA ,  Nagaraj Reddy ANAKALA ,  Subba Reddy KALLAM ,  Venkat MATTELA

    IPC: H04L12/12

    Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.

    Optimization For Angle Of Arrival And Angle Of Departure Detection
    118.
    发明申请
    Optimization For Angle Of Arrival And Angle Of Departure Detection 审中-公开

    公开(公告)号：US20200309891A1

    公开(公告)日：2020-10-01

    申请号：US16364482

    申请日：2019-03-26

    Applicant: Silicon Laboratories Inc.

    Inventor： Joel Kauppo ,  Sauli Johannes Lehtimaki ,  Antonio Torrini

    IPC: G01S3/12 ,  G01S3/46 ,  G06F17/16 ,  G06F7/483

    Abstract: An optimized system and method for determining an angle of arrival or angle of departure is disclosed. A coarse pre-search is performed to identify the general location of the incoming signal. Based on this information, a high-resolution search is performed at the general location identified in the coarse pre-search. This multi-stage approach significantly reduces the number of computations that must be performed by the device, and also reduces the amount of memory that is required to store the results of the computations. For example, a full scan may require the computations to be performed over 32,000 times. Through use of this approach, the number of computations may be reduced by over 97%. This is a similar reduction in computation time and in the amount of memory consumed by this method.

    Countermeasure for power injection security attack
    119.
    发明授权
    Countermeasure for power injection security attack 有权

    公开(公告)号：US10785016B2

    公开(公告)日：2020-09-22

    申请号：US16044727

    申请日：2018-07-25

    Applicant: Silicon Laboratories Inc.

    Inventor： DeWitt Clinton Seward

    IPC: G06F12/14 ,  H04L9/00 ,  G05F1/625

    Abstract: A system and method for determining whether a cryptographic system is being observed for power consumption analysis in an attempt to decipher secret keys. The system comprises a first external connection to receive an input voltage, an internal voltage regulator with an external capacitor to produce the desired voltage for the cryptographic system. The internal voltage regulator typically includes a switch that passes current from the first external connection to the external capacitor. By monitoring the frequency at which the switch is activated, it is possible to detect that an external voltage is being applied to the external capacitor. This external voltage is typically used to perform SPA or DPA operations. Thus, the cryptographic system may cease performing any encryption or decryption operations if an external voltage is detected.

    Load compensation to reduce deterministic jitter in clock applications
    120.
    发明授权
    Load compensation to reduce deterministic jitter in clock applications 有权

    公开(公告)号：US10778230B2

    公开(公告)日：2020-09-15

    申请号：US16661049

    申请日：2019-10-23

    Applicant: Silicon Laboratories Inc.

    Inventor： Aaron J. Caffee ,  Brian G. Drost

    IPC: H03K23/66 ,  H03K21/02

    Abstract: A method for reducing deterministic jitter in a clock generator includes providing a load current through a regulated voltage node to a circuit responsive to a divide ratio. The method includes providing an auxiliary current through the regulated voltage node. The auxiliary current has a first current level during a first period corresponding to a first value of the divide ratio and the auxiliary current has a second current level during a second period corresponding to a second value of the divide ratio.

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