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公开(公告)号:US20230251915A1
公开(公告)日:2023-08-10
申请号:US18126803
申请日:2023-03-27
Applicant: Intel Corporation
Inventor: Vadim Sukhomlinov , Kshitij A. Doshi
CPC classification number: G06F9/541 , G06F9/5072 , G06F9/5038
Abstract: A computing apparatus, including: a hardware computing platform; and logic to operate on the hardware computing platform, configured to: receive a microservice instance registration for a microservice accelerator, wherein the registration includes a microservice that the microservice accelerator is configured to provide, and a microservice connection capability indicating an ability of the microservice instance to communicate directly with other instances of the same or a different microservice; and log the registration in a microservice registration database.
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公开(公告)号:US11645127B2
公开(公告)日:2023-05-09
申请号:US17867506
申请日:2022-07-18
Applicant: Intel Corporation
Inventor: Vadim Sukhomlinov , Kshitij A. Doshi
CPC classification number: G06F9/541 , G06F9/5038 , G06F9/5072
Abstract: A computing apparatus, including: a hardware computing platform; and logic to operate on the hardware computing platform, configured to: receive a microservice instance registration for a microservice accelerator, wherein the registration includes a microservice that the microservice accelerator is configured to provide, and a microservice connection capability indicating an ability of the microservice instance to communicate directly with other instances of the same or a different microservice; and log the registration in a microservice registration database.
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公开(公告)号:US11640305B2
公开(公告)日:2023-05-02
申请号:US16524004
申请日:2019-07-26
Applicant: Intel Corporation
Inventor: Alexander Bachmutsky , Kshitij A. Doshi , Raghu Kondapalli , Vadim Sukhomlinov
IPC: G06F9/4401 , G06F3/06 , G06F9/48
Abstract: Examples are described that relate to waking up or invoking a function such as a processor-executed application or a hardware device. The application or a hardware device can specify which sources can cause wake-ups and which sources are not to cause wake-ups. A device or processor-executed software can monitor reads from or writes to a region of memory and cause the application or a hardware device to wake-up unless the wake-up is specified as inhibited. The updated region of memory can be precisely specified to allow a pinpoint retrieval of updated content instead of scanning a memory range for changes. In some cases, a write to a region of memory can include various parameters that are to be used by the woken-up application or a hardware device. Parameters can include a source of a wake-up, a timer to cap execution time, or any other information.
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114.
公开(公告)号:US11617227B2
公开(公告)日:2023-03-28
申请号:US17193537
申请日:2021-03-05
Applicant: Intel Corporation
Inventor: Raghu Kondapalli , Alexander Bachmutsky , Francesc Guim Bernat , Ned M. Smith , Kshitij A. Doshi
Abstract: Technologies for providing hardware resources as a service with direct resource addressability are disclosed. According to one embodiment of the present disclosure, a device receives a request to access a destination accelerator device in an edge network, the request specifying a destination address assigned to the destination accelerator device. The device determines, as a function of the destination address, a location of the destination accelerator device and sends the request to the destination accelerator device.
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公开(公告)号:US20230039631A1
公开(公告)日:2023-02-09
申请号:US17973268
申请日:2022-10-25
Applicant: Intel Corporation
Inventor: Francesc Guim Bernat , Da-Ming Chiang , Kshitij A. Doshi , Suraj Prabhakaran , Mark A. Schmisseur
IPC: G06F13/40 , G06F13/362 , G06N3/04 , G06F13/42 , G06F9/455 , G06N3/08 , G06F9/50 , G06F9/54 , G06N3/02
Abstract: There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an AI problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (ICL) configured to communicatively couple the first training accelerator to a second training accelerator on the first hardware platform without aid of the processor; a fabric ICL to communicatively couple the first training accelerator to a third training accelerator on a second hardware platform without aid of the processor; and a system decoder configured to operate the fabric ICL and platform ICL to share data of the accelerator hardware between the first training accelerator and second and third training accelerators without aid of the processor.
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公开(公告)号:US20220171648A1
公开(公告)日:2022-06-02
申请号:US17440701
申请日:2020-05-11
Applicant: Intel Corporation
Inventor: Bryan J. Rodriguez , Kshitij A. Doshi , Ned M. Smith , Michael G. Millsap
Abstract: In one embodiment, a computing device comprises memory circuitry and processing circuitry. The memory circuitry is to store a plurality of container images, comprising: a first container image comprising a first set of applications; and a second container image comprising a virtual machine, a guest operating system, and a second set of applications. The processing circuitry is to: instantiate a plurality of containers on a host operating system, wherein the plurality of containers comprises a first container and a second container; execute the first set of applications in the first container, wherein the first set of applications is to be executed on the host operating system; and execute the virtual machine in the second container, wherein the guest operating system is to be executed on the virtual machine and the second set of applications is to be executed on the guest operating system.
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公开(公告)号:US11345342B2
公开(公告)日:2022-05-31
申请号:US16586665
申请日:2019-09-27
Applicant: Intel Corporation
Inventor: David Gomez Gutierrez , Javier Felip Leon , Kshitij A. Doshi , Leobardo E. Campos Macias , Nilesh Amar Ahuja , Omesh Tickoo
IPC: B60W30/095 , B60W50/14 , G06V20/58 , G06V40/10
Abstract: An apparatus comprising a memory to store an observed trajectory of a pedestrian, the observed trajectory comprising a plurality of observed locations of the pedestrian over a first plurality of timesteps; and a processor to generate a predicted trajectory of the pedestrian, the predicted trajectory comprising a plurality of predicted locations of the pedestrian over the first plurality of timesteps and over a second plurality of timesteps occurring after the first plurality of timesteps; determine a likelihood of the predicted trajectory based on a comparison of the plurality of predicted locations of the pedestrian over the first plurality of timesteps and the plurality of observed locations of the pedestrian over the first plurality of timesteps; and responsive to the determined likelihood of the predicted trajectory, provide information associated with the predicted trajectory to a vehicle to warn the vehicle of a potential collision with the pedestrian.
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公开(公告)号:US20220147395A1
公开(公告)日:2022-05-12
申请号:US17584092
申请日:2022-01-25
Applicant: Intel Corporation
Inventor: Francesc Guim Bernat , Da-Ming Chiang , Kshitij A. Doshi , Suraj Prabhakaran , Mark A. Schmisseur
Abstract: There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an AI problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (ICL) configured to communicatively couple the first training accelerator to a second training accelerator on the first hardware platform without aid of the processor; a fabric ICL to communicatively couple the first training accelerator to a third training accelerator on a second hardware platform without aid of the processor; and a system decoder configured to operate the fabric ICL and platform ICL to share data of the accelerator hardware between the first training accelerator and second and third training accelerators without aid of the processor.
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公开(公告)号:US11329898B2
公开(公告)日:2022-05-10
申请号:US17202703
申请日:2021-03-16
Applicant: INTEL CORPORATION
Inventor: Francesc Guim Bernat , Kshitij A. Doshi , Daniel Rivas Barragan , Mark A. Schmisseur , Steen Larsen
IPC: G06F15/173 , H04L41/5025 , H04L43/0817 , H04L43/16 , H04L41/0896
Abstract: Embodiments may be generally directed to techniques to cause communication of a registration request between a first end-point and a second end-point of an end-to-end path, the registration request to establish resource load monitoring for one or more resources of the end-to-end path, receive one or more acknowledgements indicating resource loads for each of the one or more resources of the end-to-end path, at least one of the acknowledgements to indicate a resource of the one or more resources is not meeting a threshold requirement for the end-to-end path, and perform an action for communication traffic utilizing the one or more resources based on the acknowledgement.
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公开(公告)号:US20220121470A1
公开(公告)日:2022-04-21
申请号:US17561676
申请日:2021-12-23
Applicant: Intel Corporation
Inventor: Paritosh Saxena , Anjo Lucas Vahldiek-Oberwagner , Mona Vij , Kshitij A. Doshi , Carlos H. Morales , Clair Bowman , Marcela S. Melara , Michael Steiner
Abstract: In one embodiment, metadata associated with deployment of a container within an orchestration environment includes information indicating security preferences for deployment of the container within the orchestration environment, information indicating a level of communications between the container and other containers, and/or information indicating effects of execution of the container with respect to other containers. The metadata is used to select a particular node of a plurality of nodes within the orchestration environment on which to deploy the container based on the metadata.
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