MICROSERVICES ARCHITECTURE
    111.
    发明公开

    公开(公告)号:US20230251915A1

    公开(公告)日:2023-08-10

    申请号:US18126803

    申请日:2023-03-27

    CPC classification number: G06F9/541 G06F9/5072 G06F9/5038

    Abstract: A computing apparatus, including: a hardware computing platform; and logic to operate on the hardware computing platform, configured to: receive a microservice instance registration for a microservice accelerator, wherein the registration includes a microservice that the microservice accelerator is configured to provide, and a microservice connection capability indicating an ability of the microservice instance to communicate directly with other instances of the same or a different microservice; and log the registration in a microservice registration database.

    Microservices architecture
    112.
    发明授权

    公开(公告)号:US11645127B2

    公开(公告)日:2023-05-09

    申请号:US17867506

    申请日:2022-07-18

    CPC classification number: G06F9/541 G06F9/5038 G06F9/5072

    Abstract: A computing apparatus, including: a hardware computing platform; and logic to operate on the hardware computing platform, configured to: receive a microservice instance registration for a microservice accelerator, wherein the registration includes a microservice that the microservice accelerator is configured to provide, and a microservice connection capability indicating an ability of the microservice instance to communicate directly with other instances of the same or a different microservice; and log the registration in a microservice registration database.

    Wake-up and timer for scheduling of functions with context hints

    公开(公告)号:US11640305B2

    公开(公告)日:2023-05-02

    申请号:US16524004

    申请日:2019-07-26

    Abstract: Examples are described that relate to waking up or invoking a function such as a processor-executed application or a hardware device. The application or a hardware device can specify which sources can cause wake-ups and which sources are not to cause wake-ups. A device or processor-executed software can monitor reads from or writes to a region of memory and cause the application or a hardware device to wake-up unless the wake-up is specified as inhibited. The updated region of memory can be precisely specified to allow a pinpoint retrieval of updated content instead of scanning a memory range for changes. In some cases, a write to a region of memory can include various parameters that are to be used by the woken-up application or a hardware device. Parameters can include a source of a wake-up, a timer to cap execution time, or any other information.

    SYSTEM DECODER FOR TRAINING ACCELERATORS

    公开(公告)号:US20230039631A1

    公开(公告)日:2023-02-09

    申请号:US17973268

    申请日:2022-10-25

    Abstract: There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an AI problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (ICL) configured to communicatively couple the first training accelerator to a second training accelerator on the first hardware platform without aid of the processor; a fabric ICL to communicatively couple the first training accelerator to a third training accelerator on a second hardware platform without aid of the processor; and a system decoder configured to operate the fabric ICL and platform ICL to share data of the accelerator hardware between the first training accelerator and second and third training accelerators without aid of the processor.

    CONTAINER-FIRST ARCHITECTURE
    116.
    发明申请

    公开(公告)号:US20220171648A1

    公开(公告)日:2022-06-02

    申请号:US17440701

    申请日:2020-05-11

    Abstract: In one embodiment, a computing device comprises memory circuitry and processing circuitry. The memory circuitry is to store a plurality of container images, comprising: a first container image comprising a first set of applications; and a second container image comprising a virtual machine, a guest operating system, and a second set of applications. The processing circuitry is to: instantiate a plurality of containers on a host operating system, wherein the plurality of containers comprises a first container and a second container; execute the first set of applications in the first container, wherein the first set of applications is to be executed on the host operating system; and execute the virtual machine in the second container, wherein the guest operating system is to be executed on the virtual machine and the second set of applications is to be executed on the guest operating system.

    Potential collision warning system based on road user intent prediction

    公开(公告)号:US11345342B2

    公开(公告)日:2022-05-31

    申请号:US16586665

    申请日:2019-09-27

    Abstract: An apparatus comprising a memory to store an observed trajectory of a pedestrian, the observed trajectory comprising a plurality of observed locations of the pedestrian over a first plurality of timesteps; and a processor to generate a predicted trajectory of the pedestrian, the predicted trajectory comprising a plurality of predicted locations of the pedestrian over the first plurality of timesteps and over a second plurality of timesteps occurring after the first plurality of timesteps; determine a likelihood of the predicted trajectory based on a comparison of the plurality of predicted locations of the pedestrian over the first plurality of timesteps and the plurality of observed locations of the pedestrian over the first plurality of timesteps; and responsive to the determined likelihood of the predicted trajectory, provide information associated with the predicted trajectory to a vehicle to warn the vehicle of a potential collision with the pedestrian.

    SYSTEM DECODER FOR TRAINING ACCELERATORS

    公开(公告)号:US20220147395A1

    公开(公告)日:2022-05-12

    申请号:US17584092

    申请日:2022-01-25

    Abstract: There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an AI problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (ICL) configured to communicatively couple the first training accelerator to a second training accelerator on the first hardware platform without aid of the processor; a fabric ICL to communicatively couple the first training accelerator to a third training accelerator on a second hardware platform without aid of the processor; and a system decoder configured to operate the fabric ICL and platform ICL to share data of the accelerator hardware between the first training accelerator and second and third training accelerators without aid of the processor.

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