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    THIN WAFER HANDLING
    112.
    发明申请
    THIN WAFER HANDLING 有权
    薄膜处理

    公开(公告)号：US20140179061A1

    公开(公告)日：2014-06-26

    申请号：US13722340

    申请日：2012-12-20

    Applicant: INVENSAS CORPORATION

    Inventor： Belgacem Haba ,  Ilyas Mohammed

    IPC: H01L21/56 ,  H01L21/50

    CPC classification number: H01L21/56 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/50 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3107 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A first area of a first surface of an encapsulated component can be thinned, the component including: a semiconductor chip having an active surface opposite the first surface, and an encapsulant extending outwardly from edges of the semiconductor chip. An entire area of the active surface may be aligned with the first area. After the abrading, a second area of the encapsulated component beyond the first area may have a thickness greater than a thickness of the first area. The second area can be configured to fully support the abraded encapsulated component in a state of the encapsulated component being manipulated by handling equipment.

    Abstract translation: 封装部件的第一表面的第一区域可以变薄，所述部件包括：具有与第一表面相对的有效表面的半导体芯片以及从半导体芯片的边缘向外延伸的密封剂。 有源表面的整个区域可以与第一区域对齐。 在研磨之后，超过第一区域的包封组分的第二区域可以具有大于第一区域的厚度的厚度。 第二区域可以被配置为在被处理设备操纵的封装部件的状态下完全支撑磨损的封装部件。

    MIXED EXPOSURE FOR LARGE DIE
    114.
    发明申请
    MIXED EXPOSURE FOR LARGE DIE 有权

    公开(公告)号：US20220216180A1

    公开(公告)日：2022-07-07

    申请号：US17579259

    申请日：2022-01-19

    Applicant: Invensas Corporation

    Inventor： Javier A. Delacruz ,  Belgacem Haba

    IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L21/68

    Abstract: Techniques and arrangements for performing exposure operations on a wafer utilizing both a stepper apparatus and an aligner apparatus. The exposure operations are performed with respect to large composite base dies, e.g., interposers, defined within the wafer, where the interposers will become a part of microelectronic devices by coupling with active dies or microchips. The composite base dies may be coupled to the active dies via “native interconnects” utilizing direct bonding techniques. The stepper apparatus may be used to perform exposure operations on active regions of the composite base dies to provide a fine pitch for the native interconnects, while the aligner apparatus may be used to perform exposure operations on inactive regions of the composite base dies to provide a coarse pitch for interfaces with passive regions of the composite base dies.

    STRETCHABLE FILM ASSEMBLY WITH CONDUCTIVE TRACES
    117.
    发明申请
    STRETCHABLE FILM ASSEMBLY WITH CONDUCTIVE TRACES 有权

    公开(公告)号：US20210181511A1

    公开(公告)日：2021-06-17

    申请号：US17182016

    申请日：2021-02-22

    Applicant: Invensas Corporation

    Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Gabriel Z. Guevara ,  Min Tao

    IPC: G02B27/01

    Abstract: Apparatus and method relating generally to electronics are disclosed. In one such an apparatus, a film assembly has an upper surface and a lower surface opposite the upper surface. A dielectric film of the film assembly has a structured profile along the upper surface or the lower surface for having alternating ridges and grooves in a corrugated section in an at rest state of the film assembly. Conductive traces of the film assembly conform to the upper surface or the lower surface in or on the dielectric film in the corrugated section.

    Ultrathin layer for forming a capacitive interface between joined integrated circuit component
    119.
    发明授权
    Ultrathin layer for forming a capacitive interface between joined integrated circuit component 有权

    公开(公告)号：US10600760B2

    公开(公告)日：2020-03-24

    申请号：US16020654

    申请日：2018-06-27

    Applicant: Invensas Corporation

    Inventor： Belgacem Haba ,  Arkalgud R. Sitaram

    IPC: H01L25/065 ,  H01L23/64 ,  H01L23/48 ,  H01L21/02 ,  H01L21/311 ,  H01L25/00 ,  H01L23/00

    Abstract: Capacitive coupling of integrated circuit die components and other conductive areas is provided. Each component to be coupled has a surface that includes at least one conductive area, such as a metal pad or plate. An ultrathin layer of dielectric is formed on at least one surface to be coupled. When the two components, e.g., one from each die, are permanently contacted together, the ultrathin layer of dielectric remains between the two surfaces, forming a capacitor or capacitive interface between the conductive areas of each respective component. The ultrathin layer of dielectric may be composed of multiple layers of various dielectrics, but in one implementation, the overall thickness is less than approximately 50 nanometers. The capacitance per unit area of the capacitive interface formed depends on the particular dielectric constants κ of the dielectric materials employed in the ultrathin layer and their respective thicknesses. Electrical and grounding connections can be made at the edge of the coupled stack.

    Methods of forming flipped RF filter components
    120.
    发明授权
    Methods of forming flipped RF filter components 有权

    公开(公告)号：US10535909B2

    公开(公告)日：2020-01-14

    申请号：US16133070

    申请日：2018-09-17

    Applicant: Invensas Corporation

    Inventor： Shaowu Huang ,  Belgacem Haba

    IPC: H05K1/18 ,  H01P1/203 ,  H05K1/16 ,  H01P11/00 ,  H05K1/02 ,  H05K3/46

    Abstract: Methods of forming flipped radio frequency (RF) filter components are provided. An example method for miniaturizing conventional planar RF filters comprises: determining radio frequency (RF) filtering characteristics of a conventional planar microstrip RF filter or a conventional stripline RF filter, determining distributed RF filter elements for emulating the RF filtering characteristics of the conventional planar microstrip RF filter or the conventional stripline RF filter, creating each distributed RF filter element on a substrate, laminating a stack of the distributed RF filter elements into a single solid RF filter module; and mounting the single solid RF filter module on a horizontal substrate to vertically dispose the distributed RF filter elements of the stack. The methods create laminated stacks of distributed RF filter elements that provide a dramatic reduction in size over the horizontal planar RF filters that they replace. Deposited conductive traces of an example flipped RF filter stack provide various stub configurations of an RF filter and emulate various distributed filter elements and their configuration geometries.

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