公开(公告)号：US09412745B1

公开(公告)日：2016-08-09

申请号：US14620212

申请日：2015-02-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L29/66 ,  H01L27/32 ,  H01L27/11 ,  H01L29/78 ,  H01L29/06 ,  H01L23/535

CPC classification number: H01L27/1104 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L27/3223 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor structure is provided, including a substrate, a plurality of first semiconductor devices, a plurality of second semiconductor devices, and a plurality of dummy slot contacts. The substrate has a device region, wherein the device region includes a first functional region and a second functional region, and a dummy region is disposed therebetween. The first semiconductor devices and a plurality of first slot contacts are disposed in the first functional region. The second semiconductor devices and a plurality of second slot contacts are disposed in the second functional region. The dummy slot contacts are disposed in the dummy region.

Abstract translation: 提供一种半导体结构，包括基板，多个第一半导体器件，多个第二半导体器件和多个虚拟插槽触点。 衬底具有器件区域，其中器件区域包括第一功能区域和第二功能区域，并且虚设区域设置在其间。 第一半导体器件和多个第一时隙触点设置在第一功能区域中。 第二半导体器件和多个第二槽触点设置在第二功能区域中。 虚拟插槽触点设置在虚拟区域中。

公开(公告)号：US20160204103A1

公开(公告)日：2016-07-14

申请号：US14611843

申请日：2015-02-02

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L27/08

CPC classification number: H01L27/0802 ,  H01L27/0629 ,  H01L27/0647 ,  H01L28/20

Abstract: A semiconductor device structure having at least one thin-film resistor structure is provided. Through the metal plug(s) or metal wirings located on different layers, a plurality of stripe segments of the thin-film resistor structure is electrically connected to ensure the thin-film resistor structure with the predetermined resistance and less averting areas in the layout design.

Abstract translation: 提供具有至少一个薄膜电阻器结构的半导体器件结构。 通过位于不同层上的金属插头或金属布线，薄膜电阻器结构的多个条形段电连接，以确保具有预定电阻的薄膜电阻器结构和布局设计中较少的避免区域 。

公开(公告)号：US20160141207A1

公开(公告)日：2016-05-19

申请号：US15008453

申请日：2016-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Chieh-Te Chen

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/283 ,  H01L29/45 ,  H01L29/417 ,  H01L21/321

CPC classification number: H01L21/76897 ,  H01L21/283 ,  H01L21/32115 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method of forming a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate.

Abstract translation: 本发明提供一种形成包括基板，晶体管，第一ILD层，第二ILD层，第一接触插塞，第二接触插塞和第三接触插塞的半导体结构的方法。 晶体管设置在衬底上并且包括栅极和源极/漏极区域。 第一ILD层设置在晶体管上。 第一接触插塞设置在第一ILD层中，并且第一接触插塞的顶表面高于栅极的顶表面。 第二ILD层设置在第一ILD层上。 第二接触插塞设置在第二ILD层中并电连接到第一接触插塞。 第三接触插塞设置在第一ILD层和第二ILD层中并且电连接到栅极。

公开(公告)号：US20160104645A1

公开(公告)日：2016-04-14

申请号：US14536696

申请日：2014-11-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chien-Ting Lin ,  Shih-Fang Tzou ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/49 ,  H01L29/06 ,  H01L27/088 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/823437 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/495 ,  H01L29/4966

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a plurality of gate structures on the substrate; forming a first stop layer on the gate structures; forming a second stop layer on the first stop layer; forming a first dielectric layer on the second stop layer; forming a plurality of first openings in the first dielectric layer to expose the second stop layer; forming a plurality of second openings in the first dielectric layer and the second stop layer to expose the first stop layer; and removing part of the second stop layer and part of the first stop layer to expose the gate structures.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在所述基板上形成多个栅极结构; 在栅极结构上形成第一阻挡层; 在所述第一停止层上形成第二停止层; 在所述第二停止层上形成第一电介质层; 在所述第一电介质层中形成多个第一开口以露出所述第二阻挡层; 在所述第一介电层和所述第二停止层中形成多个第二开口以暴露所述第一停止层; 以及去除所述第二停止层的一部分和所述第一停止层的一部分以暴露所述栅极结构。

公开(公告)号：US09281199B2

公开(公告)日：2016-03-08

申请号：US14639134

申请日：2015-03-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Shih-Fang Tzou

IPC: H01L29/76 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/485

CPC classification number: H01L21/28079 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor device includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, and a bottom surface of the patterned mask layer is level with a top surface of the first interlayer dielectric. A spacer is then formed on each sidewall of the gate electrode. Subsequently, a second interlayer dielectric is formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 首先，在基板上形成第一层间电介质。 然后，在基板上形成栅电极，使得栅电极的周围被第一层间电介质包围。 之后，在栅电极上形成图案化掩模层，并且图案化掩模层的底表面与第一层间电介质的顶表面平齐。 然后在栅电极的每个侧壁上形成间隔物。 随后，形成第二层间电介质以覆盖图案化掩模层的顶表面和每个侧表面。 最后，在第一层间电介质和第二层间电介质中形成自对准接触结构。

公开(公告)号：US09269811B2

公开(公告)日：2016-02-23

申请号：US14583211

申请日：2014-12-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ling-Chun Chou ,  I-Chang Wang ,  Ching-Wen Hung

IPC: H01L31/119 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: A manufacturing method for a semiconductor device includes providing a substrate having at least agate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.

Abstract translation: 一种用于半导体器件的制造方法，包括提供至少具有玛瑙结构的基板和形成在栅极结构的侧壁上的第一间隔物，进行离子注入以将掺杂剂注入衬底中，形成具有至少一个碳 所述含碳层与所述第一间隔物接触，并进行热处理以在所述含碳层和所述第一间隔物之间​​形成保护层。

公开(公告)号：US20160013104A1

公开(公告)日：2016-01-14

申请号：US14455939

申请日：2014-08-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Ching-Ling Lin ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chun-Hsien Lin

IPC: H01L21/768 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/665 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one metal gate thereon, a source/drain region adjacent to two sides of the at least one metal gate, and an interlayer dielectric (ILD) layer around the at least one metal gate; forming a plurality of contact holes in the ILD layer to expose the source/drain region; forming a first metal layer in the contact holes; performing a first thermal treatment process; and performing a second thermal treatment process.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有至少一个金属栅极的衬底，与所述至少一个金属栅极的两侧相邻的源极/漏极区域以及围绕所述至少一个金属栅极的层间电介质层 ; 在所述ILD层中形成多个接触孔以暴露所述源/漏区; 在所述接触孔中形成第一金属层; 执行第一热处理过程; 并执行第二热处理过程。

公开(公告)号：US09230816B1

公开(公告)日：2016-01-05

申请号：US14629502

申请日：2015-02-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chia Chang Hsu

IPC: H01L21/285 ,  H01L29/66 ,  H01L21/324 ,  H01L21/308 ,  H01L21/28 ,  H01L21/3205

CPC classification number: H01L21/28518 ,  H01L21/28052 ,  H01L21/3081 ,  H01L21/32053 ,  H01L21/324 ,  H01L29/41791 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a dielectric layer on the gate structure and the ILD layer; forming a patterned hard mask on the dielectric layer; forming an opening in the dielectric layer and the ILD layer; performing a silicide process for forming a silicide layer in the opening; removing the patterned hard mask and un-reacted metal after the silicide process; and forming a contact plug in the opening.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底和围绕栅极结构的层间电介质（ILD）层; 在栅极结构和ILD层上形成介电层; 在介电层上形成图案化的硬掩模; 在介电层和ILD层中形成开口; 执行在开口中形成硅化物层的硅化物工艺; 在硅化物处理后去除图案化的硬掩模和未反应的金属; 并在开口中形成接触塞。

公开(公告)号：US20150228734A1

公开(公告)日：2015-08-13

申请号：US14697615

申请日：2015-04-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Chieh-Te Chen

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L23/532 ,  H01L21/283 ,  H01L21/321 ,  H01L23/528 ,  H01L29/45 ,  H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/283 ,  H01L21/32115 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same.

Abstract translation: 本发明提供了一种半导体结构，其包括衬底，晶体管，第一ILD层，第二ILD层，第一接触插塞，第二接触插塞和第三接触插塞。 晶体管设置在衬底上并且包括栅极和源极/漏极区域。 第一ILD层设置在晶体管上。 第一接触插塞设置在第一ILD层中，并且第一接触插塞的顶表面高于栅极的顶表面。 第二ILD层设置在第一ILD层上。 第二接触插塞设置在第二ILD层中并电连接到第一接触插塞。 第三接触插塞设置在第一ILD层和第二ILD层中并且电连接到栅极。 本发明还提供了制备该方法的方法。

公开(公告)号：US09093285B2

公开(公告)日：2015-07-28

申请号：US13848736

申请日：2013-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao

IPC: H01L27/108 ,  H01L27/06 ,  H01L21/28 ,  H01L49/02 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L21/28 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/1085 ,  H01L28/60 ,  H01L28/75 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/66545

Abstract: A semiconductor structure includes a metal gate, a second dielectric layer and a contact plug. The metal gate is located on a substrate and in a first dielectric layer, wherein the metal gate includes a work function metal layer having a U-shaped cross-sectional profile and a low resistivity material located on the work function metal layer. The second dielectric layer is located on the metal gate and the first dielectric layer. The contact plug is located on the second dielectric layer and in a third dielectric layer, thereby a capacitor is formed. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.

Abstract translation: 半导体结构包括金属栅极，第二电介质层和接触插塞。 金属栅极位于基板和第一电介质层中，其中金属栅极包括具有U形横截面轮廓的功函数金属层和位于功函数金属层上的低电阻率材料。 第二电介质层位于金属栅极和第一电介质层上。 接触塞位于第二电介质层上，在第三电介质层中形成电容器。 此外，本发明还提供了形成所述半导体结构的半导体工艺。