公开(公告)号：US06872902B2

公开(公告)日：2005-03-29

申请号：US10608294

申请日：2003-06-27

Applicant: Michael B. Cohn ,  Ji-Hai Xu

Inventor： Michael B. Cohn ,  Ji-Hai Xu

IPC: B81B3/00 ,  B81B7/00 ,  B81C1/00 ,  H01H59/00 ,  H01H57/00

CPC classification number: H01H59/0009 ,  B81B7/0077 ,  B81B2201/018 ,  B81B2203/0118 ,  B81B2207/093 ,  B81C1/00301 ,  B81C1/00357 ,  B81C3/001 ,  B81C2201/019 ,  B81C2203/0109 ,  B81C2203/0118 ,  B81C2203/019 ,  H01H2059/0018 ,  H01H2059/0072

Abstract: A MEMS device and method of making same is disclosed. In one embodiment, a micro-switch includes a base assembly comprising a movable structure bearing a contact pad. The base assembly is wafer-scale bonded to a lid assembly comprising an activator and a signal path. The movable structure moves within a sealed cavity formed during the bonding process. The signal path includes an input line and an output line separated by a gap, which prevents signals from propagating through the micro-switch when the switch is deactivated. In operation, a signal is launched into the signal path. When the micro-switch is activated, a force is established by the actuator, which pulls a portion of the movable structure upwards towards the gap in the signal path, until the contact pad bridges the gap between the input line and output line, allowing the signal to propagate through the micro-switch. Prior to bonding, the MEMS structures are annealed on a first wafer and the conductive traces and other metals are annealed on a second wafer to allow each wafer to be processed separately using different processes, e.g., different annealing temperatures.

Abstract translation: 公开了MEMS器件及其制造方法。 在一个实施例中，微型开关包括基座组件，其包括承载接触垫的可移动结构。 基座组件被晶片刻度结合到包括激活器和信号路径的盖组件。 可移动结构在接合过程中形成的密封空腔内移动。 信号路径包括输入线和由间隙分开的输出线，当开关被去激活时，该线路防止信号通过微型开关传播。 在操作中，信号被发送到信号路径中。 当微动开关被激活时，致动器建立一个力，致动器将可移动结构的一部分朝向信号路径中的间隙向上拉，直到接触垫桥接输入线和输出线之间的间隙，从而允许 信号通过微型开关传播。 在结合之前，MEMS结构在第一晶片上退火，并且导电迹线和其它金属在第二晶片上进行退火，以允许使用不同工艺（例如不同的退火温度）分别对每个晶片进行加工。

公开(公告)号：US20050042790A1

公开(公告)日：2005-02-24

申请号：US10946045

申请日：2004-09-21

Applicant: Qing Ma

Inventor： Qing Ma

IPC: B81B7/00 ,  H01L21/00

CPC classification number: B81C1/0023 ,  B81C2201/019 ,  B81C2203/019 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A method of fabricating an integrated circuit that includes a microelectromechanical (MEMS) device. The method includes forming a MEMS device on a substrate and forming an integrated circuit. The method further includes coupling the substrate to the integrated circuit to form a sealed cavity that includes the MEMS device. The substrate and the integrated circuit are coupled together in a controlled environment to establish a controlled environment within the cavity where the MEMS device is located.

Abstract translation: 一种制造包括微机电（MEMS）器件的集成电路的方法。 该方法包括在衬底上形成MEMS器件并形成集成电路。 该方法还包括将衬底耦合到集成电路以形成包括MEMS器件的密封腔。 衬底和集成电路在受控的环境中耦合在一起，以在MEMS器件所在的空腔内建立受控的环境。

公开(公告)号：US06841453B2

公开(公告)日：2005-01-11

申请号：US10037485

申请日：2001-12-19

Applicant: Ubaldo Mastromatteo

Inventor： Ubaldo Mastromatteo

IPC: B81C1/00 ,  B81C3/00 ,  H01L21/60 ,  H01L21/98 ,  H01L21/46 ,  H01L21/44 ,  H01L21/4763

CPC classification number: B81C1/00238 ,  B81C2201/019 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13144 ,  H01L2224/45144 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05684

Abstract: A process for manufacturing an integrated device comprises the steps of: forming, in a first wafer of semiconductor material, integrated structures including semiconductor regions and isolation regions; forming, on a second wafer of semiconductor material, interconnection structures of a metal material including plug elements having at least one bonding region of a metal material capable of reacting with the semiconductor regions of the first wafer; and bonding the first and second wafers together by causing the bonding regions of the plug elements to react directly with the semiconductor regions so as to form a metal silicide. Thereby, the metallurgical operations for forming the interconnection structures are completely independent of the operations required for processing silicon, so that there is no interference whatsoever between the two sets of operations. In addition, the areas where the two wafers are made may be separate, and the interconnection structures may be made with materials incompatible with silicon processing, without any risk of contamination.

Abstract translation: 一种用于制造集成器件的方法包括以下步骤：在半导体材料的第一晶片中形成包括半导体区域和隔离区域的集成结构; 在半导体材料的第二晶片上形成包括具有能够与第一晶片的半导体区域反应的金属材料的至少一个结合区域的插塞元件的金属材料的互连结构; 以及通过使所述插塞元件的接合区域与所述半导体区域直接反应从而形成金属硅化物，将所述第一和第二晶片接合在一起。 因此，用于形成互连结构的冶金操作完全独立于处理硅所需的操作，使得在两组操作之间不存在任何干扰。 此外，制造两个晶片的区域可以是分开的，并且互连结构可以由与硅加工不相容的材料制成，而没有任何污染的风险。

公开(公告)号：US20040262257A1

公开(公告)日：2004-12-30

申请号：US10862593

申请日：2004-06-07

Inventor： Richard D. Harris ,  Robert J. Kretschmann ,  Michael J. Knieser ,  Mark A. Lucak

IPC: H01B013/00

CPC classification number: B81C1/00484 ,  B81B2201/0235 ,  B81B2203/0315 ,  B81C1/00626 ,  B81C2201/019 ,  B81C2203/0109 ,  H01G5/40

Abstract: A method for fabricating an electrically isolated MEMS device having an outer stationary MEMS element and an inner movable MEMS element is provided that does not use a sacrificial layer. Rather, a pair of spacers are defined on the outer portions of the upper surface of a conductive wafer, and an insulating material is deposited thereon. The spacers are attached to a substrate to define an internal void therein. The wafer is then patterned to form the outer MEMS element as well as a conductive member for the inner MEMS element, separated from the outer MEMS element by a gap. A portion of the insulating layer that is disposed in the gap is then removed, thereby releasing the inner MEMS element from the stationary MEMS element.

Abstract translation: 提供了一种用于制造具有外部固定MEMS元件和内部可移动MEMS元件的电隔离MEMS器件的方法，其不使用牺牲层。 相反，在导电晶片的上表面的外部部分限定一对间隔物，并且在其上沉积绝缘材料。 间隔件附接到基底以在其中限定内部空隙。 然后将晶片图案化以形成外MEMS元件以及用于内部MEMS元件的导电构件，其通过间隙与外部MEMS元件分离。 然后去除设置在间隙中的绝缘层的一部分，从而将内部MEMS元件从固定MEMS元件释放。

公开(公告)号：US06835587B2

公开(公告)日：2004-12-28

申请号：US10639289

申请日：2003-08-11

Applicant: Randall L. Kubena ,  David T. Chang

Inventor： Randall L. Kubena ,  David T. Chang

IPC: H01L2100

CPC classification number: B81C3/002 ,  B81B2201/0242 ,  B81B2201/025 ,  B81C2201/019 ,  B81C2203/036 ,  B81C2203/058 ,  G01C19/5656 ,  G01P15/0802 ,  G01P15/0894 ,  G01P15/18 ,  G01P2015/084 ,  G01P2015/0842 ,  H01H1/0036 ,  H01H59/0009

Abstract: A first axis MEM tunneling/capacitive sensor and method of making same. Cantilever beam structures for at least two orthogonally arranged sensors and associated mating structures are defined on a first substrate or wafer, the at least two orthogonally arrange sensors having orthogonal directions of sensor sensitivity. A resonator structure of at least a third sensor is also defined, the third sensor being sensitive in a third direction orthogonal to the orthogonal directions of sensor sensitivity of the two orthogonally arranged sensors and the resonator structure having a mating structure thereon. Contact structures for at least two orthogonally arranged sensors are formed together with mating structures on a second substrate or wafer, the mating structures on the second substrate or wafer being of a complementary shape to the mating structures on the first substrate or wafer.

Abstract translation: 第一轴MEM隧道/电容传感器及其制造方法。 至少两个正交布置的传感器和相关联的配合结构的悬臂梁结构被限定在第一基板或晶片上，所述至少两个正交布置的传感器具有传感器灵敏度的正交方向。 还限定了至少第三传感器的谐振器结构，第三传感器在正交于两个正交布置的传感器的传感器灵敏度的正交方向的第三方向和在其上具有匹配结构的谐振器结构的灵敏度。 至少两个正交布置的传感器的接触结构与第二衬底或晶片上的配合结构一起形成，第二衬底或晶片上的配合结构与第一衬底或晶片上的配合结构互补形状。

公开(公告)号：US20040253794A1

公开(公告)日：2004-12-16

申请号：US10793653

申请日：2004-03-04

Inventor： Sadeg M. Faris

IPC: H01L021/30 ,  H01L023/495

CPC classification number: B81C1/00238 ,  B81C1/0038 ,  B81C2201/019 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to micro electromechanical systems (MEMS) and production methods thereof, and more particularly to vertically integrated MEMS systems. Manufacturing of MEMS and vertically integrated MEMS is facilitated by forming, preferably on a wafer level, plural MEMS on a MEMS layer selectively bonded to a substrate, and removing the MEMS layer intact.

Abstract translation: 本发明涉及微机电系统（MEMS）及其制造方法，更具体地涉及垂直集成的MEMS系统。 MEMS和垂直集成MEMS的制造通过优选在晶片级上在选择性地结合到衬底的MEMS层上形成多个MEMS并且完整地去除MEMS层来促进。

公开(公告)号：US20040251539A1

公开(公告)日：2004-12-16

申请号：US10801065

申请日：2004-03-15

Inventor： Sadeg M. Faris ,  Jaujeng Lin

IPC: H01L035/34

CPC classification number: B81C1/00071 ,  B81C2201/019 ,  B81C2201/0191

Abstract: A novel thermoelectric cooler array and method of making the same are disclosed. The thermoelectric cooler array is a multistage thermoelectric cooler which provides a cascaded configuration for providing heat transfer from a cold sink to a heat sink. The multistage configuration provides for much higher heat transfer range and further provides benefit of thermoelectric cooling integrated with active electronic or optoelectronic components. The method of manufacturing the thermoelectric cooling array provides for n-type and p-type thermoelectric material substrates to be selectively bonded and sliced to create the desired stages of the multistage thermoelectric cooler.

Abstract translation: 公开了一种新型的热电冷却器阵列及其制造方法。 热电冷却器阵列是多级热电冷却器，其提供级联配置，用于提供从冷水槽到散热器的热传递。 多级配置提供更高的传热范围，并进一步提供与主动电子或光电子部件集成的热电冷却的优势。 制造热电冷却阵列的方法提供n型和p型热电材料基板，以选择性地粘合和切片以产生多级热电冷却器的期望的阶段。

公开(公告)号：US20040245521A1

公开(公告)日：2004-12-09

申请号：US10800148

申请日：2004-03-12

Inventor： Sadeg M. Faris

IPC: H01L035/24

CPC classification number: B81C1/00071 ,  B81C1/0038 ,  B81C2201/019 ,  B81C2201/0191

Abstract: A novel method of manufactring a microchannel plate (nullMCPnull) is disclosed. The method comprises the steps of ion implantation of a substrate, the subsequent formation of channels paterned on the surface of the substrate and bonding of the subsequent substrate to a handle wafer. The layers are subsequently cleaved and the steps repeated until a MCP structure is achieved. The resulting MCP structure is cost-effective as compared to conventional manufacturing processes and the resulting MCP structure exhibits a funneling effect. The MCP structure may also be used for optical signal amplification for a biochip array.

Abstract translation: 公开了一种制造微通道板（“MCP”）的新颖方法。 该方法包括以下步骤：衬底的离子注入，随后形成在衬底的表面上引导的通道并将随后的衬底接合到处理晶片。 这些层随后被切割，并重复这些步骤，直到达到MCP结构。 所得到的MCP结构与传统的制造工艺相比具有成本效益，并且所得到的MCP结构表现出漏斗效应。 MCP结构也可用于生物芯片阵列的光信号放大。

公开(公告)号：US06828674B2

公开(公告)日：2004-12-07

申请号：US10164064

申请日：2002-06-05

Applicant: Maurice Karpman

Inventor： Maurice Karpman

IPC: H01L2318

CPC classification number: B81B7/007 ,  B81C1/00357 ,  B81C2201/019 ,  H01L23/10 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/16235 ,  H01L2924/181 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A hermetically sealed wafer scale package for micro-electrical-mechanical systems devices. The package consists of a substrate wafer which contains a microstructure and a cap wafer which contains other circuitry and electrical connectors to connect to external applications. The wafers are bonded together, and the microstructure sealed, with a sealant, which in the preferred embodiment is frit glass. The wafers are electrically connected by a wire bond, which is protected by an overmold. Electrical connectors are applied to the cap wafer, which are electrically linked to the outputs and inputs of the microstructure. The final package is small, easy to manufacture and test, and more cost efficient than current hermetically sealed microstructure packages.

Abstract translation: 用于微机电系统装置的气密密封的晶片级封装。 该封装由包含微结构和盖晶片的衬底晶片组成，其包含用于连接到外部应用的其它电路和电连接器。 将晶片粘合在一起，并将微结构密封，密封剂，在优选实施方案中为密封剂，其为玻璃料。 晶片通过被二次模制保护的引线接合电连接。 电连接器被施加到盖晶片，其与微结构的输出和输入电连接。 最终的包装很小，易于制造和测试，并且比当前密封的微结构包装更具成本效益。

公开(公告)号：US20040219706A1

公开(公告)日：2004-11-04

申请号：US10858017

申请日：2004-06-01

Inventor： Chang-Fegn Wan

IPC: H01L021/46 ,  H01L021/00 ,  H01L021/44 ,  H01L021/48

CPC classification number: G01L9/0042 ,  B81B2201/0264 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2203/0384 ,  B81B2207/07 ,  B81C1/00095 ,  B81C1/00285 ,  B81C1/00333 ,  B81C2201/019 ,  G01J3/26 ,  H01L29/82

Abstract: A system and method for manufacturing micro cavities at the wafer level using a unique, innovative MEMS (MicroElectroMechanical Systems) process, wherein micro cavities are formed, with epoxy bonded single-crystalline silicon membrane as cap and deposited and/or electroplated metal as sidewall, on substrate wafers. The epoxy is also the sacrificial layer. It is totally removed from within the cavity through small etch access holes etched in the silicon cap before the etch access holes are sealed under vacuum. The micro cavities manufactured therein can be used as pressure sensors or for packaging MEMS devices under vacuum or inert environment. In addition, the silicon membrane manufactured therein can be used to manufacture RF switches.

Abstract translation: 一种使用独特的创新MEMS（微电子机械系统）工艺在晶片级制造微腔的系统和方法，其中形成微腔，其中环氧键合单晶硅膜作为盖并且沉积和/或电镀金属作为侧壁， 在衬底晶圆上。 环氧树脂也是牺牲层。 在蚀刻访问孔在真空下密封之前，通过蚀刻在硅帽中的小蚀刻访问孔，完全从腔内移除。 其中制造的微孔可用作压力传感器或用于在真空或惰性环境下包装MEMS器件。 此外，其中制造的硅膜可以用于制造RF开关。