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    Enhanced-Reliability Printed Circuit Board for Tight-Pitch Components
    111.
    发明申请
    Enhanced-Reliability Printed Circuit Board for Tight-Pitch Components 有权
    用于紧密零部件的增强型可靠性印刷电路板

    公开(公告)号：US20080014419A1

    公开(公告)日：2008-01-17

    申请号：US11457492

    申请日：2006-07-14

    Applicant: Bruce John Chamberlin ,  Mitchell G. Ferrill ,  Roger Scott Krabbenhoft

    Inventor： Bruce John Chamberlin ,  Mitchell G. Ferrill ,  Roger Scott Krabbenhoft

    IPC: B32B3/00

    CPC classification number: H05K1/0366 ,  H05K1/0256 ,  H05K2201/029 ,  H05K2201/0769 ,  H05K2201/09227 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917

    Abstract: A printed circuit board is fabricated so contacts for tight-pitch components are at an angle with respect to the bundles of glass fibers in the epoxy-glass printed circuit board such that adjacent component contacts do not contact the same bundle of glass fibers. This angle may be accomplished by manufacturing a printed circuit board panel with the glass fibers at an angle with respect to its edges. This angle may also be accomplished by placing parts on a printed circuit board panel that has a traditional X-Y orthogonal weave of glass fiber bundles at an angle with respect to the edges of the panel. This angle may also be accomplished by starting with a traditional panel that has an X-Y orthogonal weave, laying out parts on the panel along the X-Y weave, then placing components on the parts at an angle with respect to the edges of the parts.

    Abstract translation: 制造印刷电路板，使得用于紧密间距部件的触点相对于环氧玻璃印刷电路板中的玻璃纤维束成一定角度，使得相邻部件触点不接触相同的玻璃纤维束。 该角度可以通过制造具有相对于其边缘成一定角度的玻璃纤维的印刷电路板面板来实现。 该角度也可以通过将部件放置在印刷电路板面板上，该印刷电路板面板具有相对于面板边缘成一定角度的玻璃纤维束的传统X-Y正交编织。 该角度也可以通过从具有X-Y正交织构的传统面板开始，沿着X-Y编织在面板上铺设部件，然后将部件相对于部件的边缘成一定角度放置在零件上。

    Multi-phase coatings for inhibiting tin whisker growth and methods of making and using the same
    112.
    发明申请
    Multi-phase coatings for inhibiting tin whisker growth and methods of making and using the same 审中-公开
    用于抑制锡晶须生长的多相涂层及其制备和使用方法

    公开(公告)号：US20070287023A1

    公开(公告)日：2007-12-13

    申请号：US11515116

    申请日：2006-08-31

    Applicant: Merrill M. Jackson ,  David Humphrey

    Inventor： Merrill M. Jackson ,  David Humphrey

    IPC: B21D39/00

    CPC classification number: H01L23/49894 ,  C23C26/00 ,  C23C28/00 ,  C25D5/48 ,  C25D7/00 ,  H01L2924/0002 ,  H05K3/244 ,  H05K3/282 ,  H05K2201/0116 ,  H05K2201/0769 ,  Y10T428/12556 ,  H01L2924/00

    Abstract: An electrical component includes a conductive substrate, a tin layer formed on the substrate, and a multi-phase coating formed on the tin layer to impede tin whisker growth. The multi-phase coating comprises a polymer matrix having pores dispersed therethrough, with the pores constituting at least 30% by volume of the coating. To form the multi-phase coating, the tin plating or finish is covered with a coating comprising a polymer matrix having a second material mixed therein. The second material is subsequently removed from the polymer matrix to produce a coating having pores in the matrix where the second material was disposed before being removed.

    Abstract translation: 电气部件包括导电基板，形成在基板上的锡层和形成在锡层上以阻止锡晶须生长的多相涂层。 多相涂层包括具有分散在其中的孔的聚合物基质，孔隙占涂层的至少30体积％。 为了形成多相涂层，用包含混合有第二材料的聚合物基质的涂层覆盖镀锡或者表面。 随后从聚合物基质中除去第二种材料以产生在基质中具有孔的涂层，其中第二种材料在被去除之前被布置。

    Wired circuit board
    113.
    发明申请
    Wired circuit board 有权
    有线电路板

    公开(公告)号：US20070051534A1

    公开(公告)日：2007-03-08

    申请号：US11514963

    申请日：2006-09-05

    Applicant: Jun Ishii ,  Yasuhito Funada ,  Yasunari Ooyabu

    Inventor： Jun Ishii ,  Yasuhito Funada ,  Yasunari Ooyabu

    IPC: H05K1/00

    CPC classification number: H05K3/28 ,  H05K1/0259 ,  H05K1/056 ,  H05K1/167 ,  H05K3/16 ,  H05K2201/0769

    Abstract: The invention provides a wired circuit board that can prevent deterioration of a conductive pattern and short-circuiting of the conductive pattern. The wired circuit board is presented herein in the form of a suspension board with circuit which comprises an insulating base layer formed on a metal supporting board, a conductive pattern formed on the insulating base layer, a metal oxide layer formed on a surface of the conductive pattern and on a surface of the insulating base layer by sputtering, and an insulating cover layer, formed on the metal oxide layer, to cover the conductive pattern. According to this suspension board with circuit, since the metal oxide layer to cover the conductive pattern is formed by the sputtering, the metal oxide layer can be formed with a uniform thickness. Hence, the metal oxide layer can fully function as a barrier layer to the conductive pattern and, accordingly, deterioration of the conductive pattern and the short-circuiting of the conductive pattern can be prevented effectively.

    Abstract translation: 本发明提供一种布线电路板，其可以防止导电图案的劣化和导电图案的短路。 布线电路板在这里以具有电路的悬挂板的形式呈现，该电路包括形成在金属支撑板上的绝缘基底层，形成在绝缘基底层上的导电图案，形成在导电的表面上的金属氧化物层 通过溅射形成在绝缘基底层的表面上，以及形成在金属氧化物层上的覆盖导电图案的绝缘覆盖层。 根据具有电路的该悬挂板，由于通过溅射形成覆盖导电图案的金属氧化物层，所以可以形成均匀的厚度的金属氧化物层。 因此，金属氧化物层可以充分发挥导电图案的阻挡层的作用，因此可以有效地防止导电图案的劣化和导电图案的短路。

    Circuit board and process for producing the same
    115.
    发明申请
    Circuit board and process for producing the same 审中-公开
    电路板及其制造方法

    公开(公告)号：US20060249304A1

    公开(公告)日：2006-11-09

    申请号：US10554660

    申请日：2004-06-30

    Applicant: Hideaki Tanaka ,  Nobuyuki Sensui

    Inventor： Hideaki Tanaka ,  Nobuyuki Sensui

    IPC: H05K1/03

    CPC classification number: H05K3/0023 ,  H05K3/26 ,  H05K3/28 ,  H05K3/4644 ,  H05K2201/0761 ,  H05K2201/0769 ,  H05K2203/0786 ,  H05K2203/0793 ,  Y10T29/49126 ,  Y10T29/49155

    Abstract: In the case of using a photosensitive insulating resin for a surface protective layer of a circuit wiring pattern, or for an insulating layer between circuit wiring conductor layers in a circuit board, Na ions adsorbed on the photosensitive insulating resin are replaced with a polyvalent metal through a treatment step containing Na ions which is executed after a heat curing step of the photosensitive insulating resin. For the polyvalent metal, a II group including Mg or Ca can be selected.

    Abstract translation: 在电路布线图案的表面保护层用感光绝缘树脂或电路基板的电路布线导体层之间的绝缘层的情况下，吸附在感光绝缘树脂上的Na离子被多价金属代替 包含在感光绝缘树脂的热固化步骤之后执行的Na离子的处理步骤。 对于多价金属，可以选择包括Mg或Ca的II族。

    Method for improving electromigration performance of metallization features through multiple depositions of binary alloys
    117.
    发明申请
    Method for improving electromigration performance of metallization features through multiple depositions of binary alloys 审中-公开
    通过二元合金多次沉积来改善金属化特征的电迁移性能的方法

    公开(公告)号：US20030217462A1

    公开(公告)日：2003-11-27

    申请号：US10021994

    申请日：2001-12-13

    Inventor： Fei Wang ,  Brian J. MacDonald ,  Amit P. Marathe ,  John E. Sanchez ,  Pin-Chin C. Wang ,  Joffre F. Bernard

    IPC: H05K001/00 ,  H05K003/00

    CPC classification number: H01L21/76843 ,  H01L21/2855 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H05K3/045 ,  H05K3/107 ,  H05K3/181 ,  H05K3/388 ,  H05K2201/0769 ,  H05K2203/0723 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  H01L2924/00

    Abstract: The reliability and electromigration performance of planarized metallization patterns in an electrical device, for example copper, inlaid in the surface of a layer of dielectric material overlying a semiconductor substrate, are enhanced by a method for more reliably and uniformly diffusing into a conductive fill alloying elements which reduce or substantially prevent electromigration. The method comprises depositing around a conductive fill metal alloy films and alloying layers comprising one or more alloying elements having physical and/or chemical attributes which are effective for minimizing or substantially preventing electromigration along grain boundaries and/or along the interface between the surfaces of the conductive fill and other surfaces. The metal alloy films and alloying layers are advantageously deposited where their particular physical and/or chemical attributes may be most beneficial for improving electromigration performance. The alloying elements may then be diffused into the conductive fill to effect alloying therewith.

    Abstract translation: 在覆盖在半导体衬底上的介电材料层的表面中的电子器件（例如铜）中的平面化金属化图案的可靠性和电迁移性能通过用于更可靠和均匀地扩散到导电填充合金元素中的方法来增强 这减少或基本上防止电迁移。 该方法包括沉积围绕导电填充金属合金膜和合金化层，其包含一种或多种具有物理和/或化学属性的合金元素，其具有对于最小化或基本上防止沿着晶界的电迁移和/或沿着晶界的表面之间的界面 导电填料等表面。 有利地沉积金属合金膜和合金层，其中其特定的物理和/或化学属性可能最有利于改善电迁移性能。 然后可以将合金元素扩散到导电填料中以实现与其的合金化。

    Via plug layout structure for connecting different metallic layers
    119.
    发明授权
    Via plug layout structure for connecting different metallic layers 失效
    通过插头布局结构连接不同的金属层

    公开(公告)号：US06483045B1

    公开(公告)日：2002-11-19

    申请号：US09626409

    申请日：2000-07-26

    Applicant: Mu-Chun Wang ,  Shih-Chieh Kao ,  Shiang Huang-Lu ,  Yuan-Chang Liu

    Inventor： Mu-Chun Wang ,  Shih-Chieh Kao ,  Shiang Huang-Lu ,  Yuan-Chang Liu

    IPC: H05K111

    CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L2924/0002 ,  H05K1/115 ,  H05K2201/0769 ,  H05K2201/0969 ,  H05K2201/0979 ,  H01L2924/00

    Abstract: A via plug layout structure for connecting different metallic layers. The structure includes a plurality of via plugs arranged in a fan-shaped pattern and a plurality of empty bars positioned between a single via plug and the fanned-out via plugs so that incoming current to the single via plug is equally distributed to every one of the fanned-out via plug and current stress in each fanned-out via plug is identical. Hence, via plugs having particularly serious electromigration problem can be discovered. In addition, single via plug having different critical dimension can be fabricated so that maximum critical dimension sustainable by the via plug is determined after an electromigration test.

    Abstract translation: 用于连接不同金属层的通孔插头布局结构。 该结构包括布置成扇形图案的多个通孔塞和位于单个通孔插头和扇形通孔之间的多个空杆，使得到单个通孔塞的进入电流被均等地分配到 通过插头的每个扇形插头中的插头和电流应力都是相同的。 因此，可以发现通过具有特别严重的电迁移问题的插头。 此外，可以制造具有不同临界尺寸的单通孔塞，使得在电迁移测试之后确定由通孔插塞可持续的最大临界尺寸。

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