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    METHODS AND APPARATUS FOR PERFORMING REED-SOLOMON ENCODING
    122.
    发明申请
    METHODS AND APPARATUS FOR PERFORMING REED-SOLOMON ENCODING 审中-公开

    公开(公告)号：US20170250713A1

    公开(公告)日：2017-08-31

    申请号：US15054395

    申请日：2016-02-26

    Applicant: Altera Corporation

    Inventor： Martin Langhammer ,  Sami Mumtaz ,  Simon Finn

    IPC: H03M13/15 ,  H03M13/00

    CPC classification number: H03M13/1515 ,  H03M13/159 ,  H03M13/616 ,  H03M13/617

    Abstract: The present embodiments relate to Reed-Solomon encoding, and to circuitry for performing such encoding, particularly in an integrated circuit. A Reed-Solomon encoder circuit may receive a message with data symbols and compute a partial syndrome vector by multiplying the data symbols with a first matrix. The Reed-Solomon encoder circuit may further compute parity check symbols by solving a system of linear equations that includes the partial syndrome vector and a second matrix. As an example, the second matrix may be decomposed into a lower triangular matrix and an upper triangular matrix, and the parity check symbols may be computed by performing a forward substitution and a backward substitution using the lower and upper triangular matrices. The Reed-Solomon encoder circuit may generate a Reed-Solomon code word by combining the data symbols and the parity check symbols, and provide the Reed-Solomon code word at an output port.

    HIGH-SPEED SERIAL DATA SIGNAL RECEIVER CIRCUITRY
    123.
    发明申请
    HIGH-SPEED SERIAL DATA SIGNAL RECEIVER CIRCUITRY 审中-公开

    公开(公告)号：US20170230209A1

    公开(公告)日：2017-08-10

    申请号：US15495622

    申请日：2017-04-24

    Applicant: Altera Corporation

    Inventor： Weiqi Ding ,  Mengchi Liu ,  Wilson Wong ,  Sergey Y. Shumarayev

    IPC: H04L25/03 ,  H04L7/00

    CPC classification number: H04L25/03885 ,  H04L7/0054 ,  H04L25/03019 ,  H04L25/03878

    Abstract: Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gbps and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

    POWER GATED LOOKUP TABLE CIRCUITRY
    124.
    发明申请
    POWER GATED LOOKUP TABLE CIRCUITRY 有权

    公开(公告)号：US20170201256A1

    公开(公告)日：2017-07-13

    申请号：US14994864

    申请日：2016-01-13

    Applicant: Altera Corporation

    Inventor： Bee Yee Ng ,  Hee Kong Phoon ,  Teik Hong Ooi ,  Guan Hoe Oh

    IPC: H03K19/177

    CPC classification number: H03K19/17728 ,  H03K19/0016 ,  H03K19/1737 ,  H03K19/1776

    Abstract: A programmable integrated circuit with lookup table circuitry is provided. The lookup table (LUT) circuitry may be formed using multiplexers. A multiplexer in the lookup table circuitry may be implemented using only tristate inverting circuits. Each tristate inverting circuit may include a first set of n-channel and p-channel transistors that receive a static control bit from a memory element and a second set of n-channel and p-channel transistors that receive true and complementary versions of a user signal. The first and second sets of transistors may be coupled in series between a positive power supply terminal and a ground power supply terminal. A LUT multiplexer implemented in this way need not include separate transmission gates at the output of each tristate inverting circuit and may exhibit minimal subthreshold leakage.

    Power gated lookup table circuitry
    125.
    发明授权
    Power gated lookup table circuitry 有权

    公开(公告)号：US09705504B1

    公开(公告)日：2017-07-11

    申请号：US14994864

    申请日：2016-01-13

    Applicant: Altera Corporation

    Inventor： Bee Yee Ng ,  Hee Kong Phoon ,  Teik Hong Ooi ,  Guan Hoe Oh

    IPC: H03K19/177

    CPC classification number: H03K19/17728 ,  H03K19/0016 ,  H03K19/1737 ,  H03K19/1776

    Abstract: A programmable integrated circuit with lookup table circuitry is provided. The lookup table (LUT) circuitry may be formed using multiplexers. A multiplexer in the lookup table circuitry may be implemented using only tristate inverting circuits. Each tristate inverting circuit may include a first set of n-channel and p-channel transistors that receive a static control bit from a memory element and a second set of n-channel and p-channel transistors that receive true and complementary versions of a user signal. The first and second sets of transistors may be coupled in series between a positive power supply terminal and a ground power supply terminal. A LUT multiplexer implemented in this way need not include separate transmission gates at the output of each tristate inverting circuit and may exhibit minimal subthreshold leakage.

    Level-sensitive two-phase single-wire latch controllers without contention
    127.
    发明授权
    Level-sensitive two-phase single-wire latch controllers without contention 有权

    公开(公告)号：US09698784B1

    公开(公告)日：2017-07-04

    申请号：US15201048

    申请日：2016-07-01

    Applicant: Altera Corporation

    Inventor： Dana How

    IPC: H03K19/00 ,  H03K19/02 ,  H03K19/0175 ,  H03K3/038

    CPC classification number: H03K19/0175 ,  G06F9/3869 ,  H03K3/038 ,  H03K19/0966

    Abstract: Systems and methods are described for a contention-free single-wire latch controller that includes first and second bidirectional signal pins (e.g., the L and R pins in the FIGS), a latch enable output pin (or signal), E, and a decision element (such as a NAND or a NOR gate). A first driving transistor may be coupled between the first bidirectional signal pin and a power rail. A second driving transistor may be coupled between the second bidirectional signal pin and the power rail. A first half-latch may be coupled to the first bidirectional signal pin. A second half-latch may be coupled to the second bidirectional signal pin.

    System reset controller replacing individual asynchronous resets
    129.
    发明授权
    System reset controller replacing individual asynchronous resets 有权

    公开(公告)号：US09685957B2

    公开(公告)日：2017-06-20

    申请号：US14249292

    申请日：2014-04-09

    Applicant: Altera Corporation

    Inventor： Dana How

    IPC: H03K19/177 ,  G06F17/50

    CPC classification number: H03K19/1774 ,  G06F17/5054

    Abstract: An integrated circuit device comprises a system reset controller. The system reset controller includes a clock signal input, a reset signal input, a clock signal output, and a reset signal output. The system reset controller is arranged to receive distributed clock and reset signal inputs and output modified clock and reset signal outputs such that asynchronous reset inputs in downstream system components can be replaced by logic elements not requiring asynchronous reset inputs with no change in externally-visible behavior except the length of reset sequences as measured by clock pulses.

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