公开(公告)号：US20150048499A1

公开(公告)日：2015-02-19

申请号：US13969240

申请日：2013-08-16

Applicant: Macrotech Technology Inc. ,  Powertech Technology Inc.

Inventor： Kuo-Jui TAI ,  Li-Jen LIN ,  Shou-Chian HSU

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L23/3192 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/05567 ,  H01L2224/11 ,  H01L2224/13013 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/14517 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: Disclosed is a fine-pitch pillar bump layout structure on chip, comprising a chip, a passivation layer and at least two pillar bumps. Bonding pads of the chip are disposed along an X-axis. Openings of the passivation layer have a first aspect ratio. Pillar bumps are disposed on the bonding pads and each has a pillar body and a solder cap. Each pillar body has a plurality of symmetrical raised blocks disposed on the passivation layer and extended in both directions of Y-axis. The pillar bodies have shrunk bump widths along the X-axis so that a second aspect ratio is at least 1.5 times greater than the first aspect ratio and to partially expose the bonding pads and to make the central points of the pillar bodies be vertically aligned with the central points of the openings of the passivation layer.

Abstract translation: 公开了一种芯片上的细间距柱状突起布局结构，包括芯片，钝化层和至少两个柱状凸块。 芯片的接合焊盘沿着X轴设置。 钝化层的开口具有第一纵横比。 柱形凸块设置在接合焊盘上，并且每个都具有柱体和焊盘。 每个柱体具有设置在钝化层上并在Y轴的两个方向上延伸的多个对称的凸起块。 柱体沿着X轴具有缩小的凸起宽度，使得第二纵横比比第一长宽比大至少1.5倍，并且部分地暴露接合焊盘并使柱体的中心点垂直对准 钝化层开口的中心点。

公开(公告)号：US08541870B1

公开(公告)日：2013-09-24

申请号：US13645289

申请日：2012-10-04

Applicant: Powertech Technology Inc.

Inventor： Wen-Jeng Fan ,  Che-Min Chu ,  Wei-Min Chen

IPC: H01L23/495

CPC classification number: H01L23/4951 ,  H01L23/49558 ,  H01L23/49575 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00

Abstract: Disclosed is a semiconductor package utilizing a tape to reinforce fixing of leads to a die pad having a through hole. The package primarily comprises a leadframe having the plurality of leads and the die pad, a tape, at least a chip, and an encapsulant. The die pad. The tape is attached beneath the leadframe adjacent to the inner fingers of the leads to fix the leads and the die pad for wire-bonding. Additionally, the tape does not completely cover the through hole. The chip is disposed on the leads and the die pad and electrically connected to the inner fingers. The encapsulant encapsulates the die pad, the tape and the chip with the leads being insulatedly bonded where the encapsulant further completely fills into the through hole through its opening without completely covered by the tape.

Abstract translation: 公开了一种利用带子来加强将引线固定到具有通孔的管芯焊盘的半导体封装。 封装主要包括具有多个引线和管芯焊盘的引线框，至少芯片和密封剂的带。 芯片垫 带子连接在引线框架的下方，与引线的内指相邻，以固定引线和芯片焊盘以进行引线接合。 此外，磁带不完全覆盖通孔。 芯片设置在引线和芯片焊盘上，并与内指电连接。 密封剂封装芯片焊盘，磁带和芯片，引线绝缘地结合在一起，其中密封剂通过其开口进一步完全填充到通孔中，而不完全被磁带覆盖。

公开(公告)号：US20250040276A1

公开(公告)日：2025-01-30

申请号：US18462398

申请日：2023-09-06

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin HSU

IPC: H01L27/146

Abstract: An image sensor package includes an image sensor chip having a chip body, a metal dam, and a transparent substrate having a surface. The chip body has an active surface including a photosensitive area and a non-sensitive area surrounding the photosensitive area. The metal dam is formed on the non-sensitive area of the active surface, surrounds a photosensitive layer formed on the photosensitive area at intervals, is electrically insulated from the chip body, and has a thickness. A glue dam is formed on the surface and is aligned with and is bonded to the metal dam. A thickness of the glue dam is less than the thickness of the metal dam. Accordingly, the metal dam and the glue dam are combined to form a dam structure, and the quantity of liquid glue to form the glue dam is decreased. Thus, the yield of the image sensor package is enhanced.

公开(公告)号：US20240313024A1

公开(公告)日：2024-09-19

申请号：US18523907

申请日：2023-11-30

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L27/14634 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/562 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A package structure including a first redistribution circuit structure, a chip, a second redistribution circuit structure, a plurality of packages, and a plurality of limiting connectors is provided. The chip is disposed on the first redistribution circuit structure. The second redistribution circuit structure is disposed on the chip. The plurality of packages are disposed on the second redistribution circuit structure. Each of the packages includes an encapsulant. The plurality of limiting connectors are disposed between each of the packages and the second redistribution circuit structure.

公开(公告)号：US12094809B2

公开(公告)日：2024-09-17

申请号：US17562211

申请日：2021-12-27

Applicant: Powertech Technology Inc.

Inventor： Hiroyuki Fujishima ,  Shang-Yu Chang-Chien

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/29 ,  H01L2224/73253 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562

Abstract: A chip-middle type fan-out panel-level package (FOPLP) has a routing layer, a polyimide layer formed on the routing layer and having a plurality of pillar openings and a chip opening, a plurality of metal pillars mounted on the routing layer through the corresponding pillar openings, a chip mounted on the first routing layer through the chip opening and a molding compound formed on the polyimide layer to encapsulate the metal pillars and the chip. The polyimide layer is used to control the warpage of the FOPLP. The polyimide layer is formed inside the FOPLP and the chip is directly mounted on the first routing layer through the chip opening, so a height of the FOPLP is not increased when the first PI layer is added.

公开(公告)号：US11990494B2

公开(公告)日：2024-05-21

申请号：US17383376

申请日：2021-07-22

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L27/14618 ,  H01L27/1462 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14689 ,  H01L27/1469

Abstract: A package structure including a first die, a second die, an encapsulant, a dam structure, a light-transmitting sheet, a conductive connector, a circuit layer, and a conductive terminal is provided. The first die includes a first active surface. The first active surface has a sensing area. The second die is arranged such that a second back surface thereof faces the first die. The encapsulant covers the second die. The encapsulant has a first encapsulating surface and a second encapsulating surface. The dam structure is located on the first encapsulating surface and exposes the sensing area. The light-transmitting sheet is located on the dam structure. The conductive connector penetrates the encapsulant. The circuit layer is located on the second encapsulating surface. The first die is electrically connected to the second die through the conductive connector and the circuit layer. The conductive terminal is disposed on the circuit layer.

公开(公告)号：US11916035B2

公开(公告)日：2024-02-27

申请号：US17392274

申请日：2021-08-03

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/73 ,  H01L24/19 ,  H01L24/20 ,  H01L24/26 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L23/481 ,  H01L24/16 ,  H01L24/24 ,  H01L24/32 ,  H01L2224/16145 ,  H01L2224/2101 ,  H01L2224/221 ,  H01L2224/24146 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73217

Abstract: A packaging structure including first, second, and third dies, an encapsulant, a circuit structure, and a filler is provided. The encapsulant covers the first die. The circuit structure is disposed on the encapsulant. The second die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die has an optical signal transmission area. The filler is disposed between the second die and the circuit structure and between the third die and the circuit structure. A groove is present on an upper surface of the circuit structure. The upper surface includes first and second areas located on opposite sides of the groove. The filler directly contacts the first area. The filler is away from the second area. A manufacturing method of a packaging structure is also provided.

公开(公告)号：US20240021595A1

公开(公告)日：2024-01-18

申请号：US18209500

申请日：2023-06-14

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Ching-Wei Liao ,  Shang-Yu Chang Chien

IPC: H01L25/16 ,  H01L23/538 ,  H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L25/167 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/5383 ,  H01L23/481 ,  H01L23/49816 ,  H01L21/4857 ,  H01L21/56 ,  H01L2224/16225 ,  H01L24/16

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a first package and a second package, and the second package is disposed on the first package. The first package includes a first redistribution layer, at least one chip and a second redistribution layer. The chip is disposed between the first redistribution layer and the second redistribution layer. The second package includes a third redistribution layer and at least three light-emitting elements. The third redistribution layer is electrically connected to the second redistribution layer, and the second redistribution layer is disposed between the chip and the third redistribution layer. The light-emitting elements are disposed on the third redistribution layer and electrically connected to the third redistribution layer. Each light-emitting element includes a first surface opposite to the third redistribution layer, and the first surfaces of the light-emitting elements are coplanar.

公开(公告)号：US11848318B2

公开(公告)日：2023-12-19

申请号：US17407174

申请日：2021-08-19

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Pei-Hsun Chou ,  Ko-Lun Liao

IPC: H01L25/18 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/32 ,  H01L2224/32145 ,  H01L2224/32225

Abstract: A package structure and a manufacturing thereof are provided. The package structure includes a base, a chip, a control element and an underfill. The chip is disposed on the base and includes a recess, and the recess has a bottom surface and a sidewall. The control element is disposed between the base and the chip and disposed on the bottom surface of the recess, and a gap exists between the control element and the sidewall of the recess. The underfill is disposed in the recess. The chip and the control element are electrically connected to the base respectively.

公开(公告)号：US20230223311A1

公开(公告)日：2023-07-13

申请号：US17840209

申请日：2022-06-14

Applicant: Powertech Technology Inc.

Inventor： Kun-Yung HUANG ,  Jen-I HUANG

IPC: H01L23/31 ,  H01L23/00

CPC classification number: H01L23/3192 ,  H01L24/05 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/02331

Abstract: A semiconductor packaging assembly includes a redistribution layered structure having a plurality of device regions and a plurality of cutting regions separating the device regions, a plurality of recess structures respectively formed in the cutting regions, a plurality of chips respectively disposed in the device regions, and an encapsulating layer formed on the redistribution layered structure to fill the recess structures and enclose the chips.