公开(公告)号：US20250040276A1

公开(公告)日：2025-01-30

申请号：US18462398

申请日：2023-09-06

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin HSU

IPC: H01L27/146

Abstract: An image sensor package includes an image sensor chip having a chip body, a metal dam, and a transparent substrate having a surface. The chip body has an active surface including a photosensitive area and a non-sensitive area surrounding the photosensitive area. The metal dam is formed on the non-sensitive area of the active surface, surrounds a photosensitive layer formed on the photosensitive area at intervals, is electrically insulated from the chip body, and has a thickness. A glue dam is formed on the surface and is aligned with and is bonded to the metal dam. A thickness of the glue dam is less than the thickness of the metal dam. Accordingly, the metal dam and the glue dam are combined to form a dam structure, and the quantity of liquid glue to form the glue dam is decreased. Thus, the yield of the image sensor package is enhanced.

公开(公告)号：US20150091154A1

公开(公告)日：2015-04-02

申请号：US14041391

申请日：2013-09-30

Applicant: Macrotech Technology Inc. ,  Powertech Technology Inc.

Inventor： Hung-Hsin HSU

IPC: H01L23/34 ,  H01L23/544

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/525 ,  H01L24/97 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: Disclosed is a substrateless semiconductor package having a plurality of scribe lines formed on a heat spreader, primarily comprising the heat spreader, a chip disposed on the heat spreader and an encapsulant. Formed on a thermally dissipating surface of the heat spreader are a plurality of scribe line grooves with a plurality of openings formed inside to penetrate through the die-attaching surface of the heat spreader. The chip is disposed on the die-attaching surface and the encapsulant is formed on the die-attaching surface to encapsulate a first surface of the chip on which a plurality of external pads are formed Without being covered by the encapsulant. Therein, the encapsulant is filled in the scribe line grooves via the openings so that a scribe line pattern exposed from the thermally dissipating surface is formed.

Abstract translation: 公开了一种无基板半导体封装，其具有形成在散热器上的多个划线，主要包括散热器，设置在散热器上的芯片和密封剂。 在散热器的散热面上形成有多个划线槽，其具有形成在内部的多个开口，以穿透散热器的模具安装面。 芯片设置在管芯附接表面上，并且密封剂形成在管芯附接表面上以封装其上形成有多个外部焊盘的芯片的第一表面，而不被密封剂覆盖。 其中，密封剂经由开口填充在划线槽中，从而形成从散热表面露出的划线图案。

公开(公告)号：US20220328422A1

公开(公告)日：2022-10-13

申请号：US17454742

申请日：2021-11-12

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu CHANG CHIEN ,  Nan-Chun LIN ,  Hung-Hsin HSU

IPC: H01L23/552 ,  H01Q1/22 ,  H01L23/66 ,  H01L21/56 ,  H01L21/762

Abstract: A fan-out semiconductor package includes: a redistribution structure; a functional chip coupled to the redistribution structure; an isolation structure disposed on the redistribution structure and including a body formed with through-holes; a shielding structure disposed on the isolation structure and the redistribution structure; a first conductive pattern structure disposed on the isolation structure and extending through the through-holes of the isolation structure; an encapsulating structure disposed on the isolation structure, the shielding structure and the first conductive pattern structure; and a second conductive pattern structure disposed on the encapsulating structure. A method for manufacturing the fan-out semiconductor package is also disclosed.

公开(公告)号：US20210050275A1

公开(公告)日：2021-02-18

申请号：US16741358

申请日：2020-01-13

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu CHANG-CHIEN ,  Hung-Hsin HSU ,  Nan-Chun LIN

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/64 ,  H01L23/00

Abstract: A fan-out semiconductor package and packaging method thereof are disclosed. In the packaging method, a photosensitive material is used to encapsulate multiple bare chips and multiple passive devices, so multiple metal pads of each bare chip and multiple metal terminals of each passive device are exposed out of the photosensitive material by a photolithography process. The exposed metal pads and the exposed metal terminals are directly and electrically connected to a redistribution layer. In the packaging method, the bare chips and the passive devices are located on the same side of the redistribution layer and encapsulated by the photosensitive material. In addition, in the packaging method, the bare chips are not processed by a wafer bump process and does not use the thinner passive devices with high cost. Therefore, a height of the fan-out semiconductor package of the present invention is decreased and a manufacturing cost is relatively reduced.

公开(公告)号：US20220302061A1

公开(公告)日：2022-09-22

申请号：US17392369

申请日：2021-08-03

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu CHANG-CHIEN ,  Hung-Hsin HSU ,  Nan-Chun LIN

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/463 ,  H01L23/488

Abstract: A semiconductor package and fabricating method thereof are disclosed. The semiconductor package has a chip, a plurality of first and second bumps, an encapsulation, a redistribution. The chip has a plurality of pads and an active area and the active surface has a first area and a second area surrounding the first area. The pads are formed on a first area of the active surface. Each first bump is formed on the corresponding pad. The second bumps are formed on the second area and each second bump has a first layer and a second layer with different widths. The encapsulation encapsulates the chip and the first and second bumps and is ground to expose the first and second bumps therefrom. During grinding, all of the first bumps are completely exposed by determining a width of an exposed surface of the second bump to electrically connect to the redistribution is increased.

公开(公告)号：US20170117263A1

公开(公告)日：2017-04-27

申请号：US15190712

申请日：2016-06-23

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Yun-Hsin YEH ,  Hung-Hsin HSU ,  Chia-Yu HUNG

IPC: H01L25/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L21/563 ,  H01L21/568 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0657 ,  H01L2021/6006 ,  H01L2021/60247 ,  H01L2021/60262 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A molded interconnecting substrate has an embedded redistribution layer (RDL), an embossed RDL, a plurality of conductive pillars encapsulated in a molding core, and a chip also encapsulated in the molded core. The conductive pillars are disposed on the external pads of the embedded RDL. The chip is die-bonded onto the embedded RDL. The molding core has an external surface and an opposing component-installing surface. The embedded RDL is embedded in the molding core from the external surface. The bottom surface of the embedded RDL is coplanar to the external surface and the pillar-top surfaces of the conductive pillars are coplanar to the component-installing surface. The embossed RDL is disposed on and extruded from the component-installing surface including a plurality of pillar-top pads aligned and bonded to the pillar-top surfaces. Accordingly, it is possible to eliminate a flip-chip molding thickness without manufacture of substrate plating lines where fine-pitch substrate circuitry can be achieved without substrate drilling process.