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公开(公告)号:US20180300933A1
公开(公告)日:2018-10-18
申请号:US15489177
申请日:2017-04-17
Applicant: Intel Corporation
Inventor: Devan Burke , Adam T. Lake , Jeffery S. Boles , John H. Feit , Karthik Vaidyanathan , Abhishek R. Appu , Joydeep Ray , Subramaniam Maiyuran , Altug Koker , Balaji Vembu , Murali Ramadoss , Prasoonkumar Surti , Eric J. Hoekstra , Gabor Liktor , Jonathan Kennedy , Slawomir Grajewski , Elmoustapha Ould-Ahmed-Vall
IPC: G06T15/00
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.
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公开(公告)号:US20180293961A1
公开(公告)日:2018-10-11
申请号:US15483748
申请日:2017-04-10
Applicant: Intel Corporation
Inventor: Hugues Labbe , Karthik Vaidyanathan , Prasoonkumar Surti , Atsuo Kuwahara , Sameer Kp , Jonathan Kennedy
Abstract: Systems and methods may provide for determining a start time for an output image scanner to begin scanning an output image to a display device, determining a processing start time for each row of blocks of image pixel data within a rasterizer to ensure its completion before each row of blocks of image pixel data within the output image begin to be scanned out, and scheduling the start of processing of each row of blocks of image pixel data. In one example, the start time for the rasterizer to process a row of blocks of image pixel data uses the number of graphical objects to rendered into the output image and the processing times required by prior images.
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公开(公告)号:US09922396B2
公开(公告)日:2018-03-20
申请号:US15157667
申请日:2016-05-18
Applicant: Intel Corporation
Inventor: Gabor Liktor , Karthik Vaidyanathan
IPC: G06T15/00 , G06T1/20 , G06T15/06 , G06F12/0871
CPC classification number: G06T1/20 , G06F12/0871 , G06F2212/1016 , G06F2212/302 , G06F2212/401 , G06T15/06 , G06T17/005
Abstract: Incremental encoding of Bounding Volume Hierarchies (BVH) enables coarse quantization of bounding volumes, significantly reducing their memory footprint. However, reducing the size of the BVH alone does not yield a comparable reduction in memory bandwidth in some embodiments. While the bounding volumes of the BVH nodes can be aggressively quantized, the size of the child node pointers remains a significant overhead. A two-level clustering method introduces a memory layout and node addressing scheme, which allows the reordering of BVH nodes to reduce their memory footprint in hardware ray tracing systems using reduced precision ray traversal.
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公开(公告)号:US09767602B2
公开(公告)日:2017-09-19
申请号:US14319472
申请日:2014-06-30
Applicant: INTEL CORPORATION
Inventor: Gabor Liktor , Marco Salvi , Karthik Vaidyanathan
IPC: G06T15/80
Abstract: Various embodiments are generally directed to techniques for reducing processing demands of shading primitives in rendering a 2D screen image from a 3D model. A device includes a clipping component to clip a visible primitive of a 2D screen image derived from of a 3D model within a first area of the screen image covered by a shading pixel to form a polygon representing an intersection of the first area and the visible primitive; a first interpolation component to interpolate at least one attribute of vertices of the visible primitive to each vertex of the polygon; and a second interpolation component to interpolate color values of the vertices of the polygon to a point within a second area covered by a screen pixel of the screen image, the second area smaller than the first area and at least partly coinciding with the first area. Other embodiments are described and claimed.
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公开(公告)号:US20170011545A1
公开(公告)日:2017-01-12
申请号:US15261893
申请日:2016-09-10
Applicant: Intel Corporation
Inventor: Carl J. Munkberg , Karthik Vaidyanathan , Jon N. Hasselgren , Franz P. Clarberg , Tomas G. Akenine-Moller , Marco Salvi
CPC classification number: G06T15/503 , G06T5/50 , G06T15/06 , G06T15/50 , G06T15/506 , G06T2200/21 , G06T2207/10052 , H04N5/23229
Abstract: Real-time light field reconstruction for defocus blur may be used to handle the case of simultaneous defocus and motion blur. By carefully introducing a few approximations, a very efficient sheared reconstruction filter is derived, which produces high quality images even for a very low number of input samples in some embodiments. The algorithm may be temporally robust, and is about two orders of magnitude faster than previous work, making it suitable for both real-time rendering and as a post-processing pass for high quality rendering in some embodiments.
Abstract translation: 用于散焦模糊的实时光场重建可用于处理同时散焦和运动模糊的情况。 通过仔细地引入几个近似值,导出非常有效的剪切重建滤波器,即使在一些实施例中对于非常低数量的输入样本也可产生高质量图像。 该算法可以在时间上是稳健的,并且比以前的工作快两个数量级,使得它在一些实施例中适合于实时渲染和用于高质量渲染的后处理通行。
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公开(公告)号:US12243125B2
公开(公告)日:2025-03-04
申请号:US18517318
申请日:2023-11-22
Applicant: Intel Corporation
Inventor: Karthik Vaidyanathan , Prasoonkumar Surti , Hugues Labbe , Atsuo Kuwahara , Sameer KP , Jonathan Kennedy , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh
Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
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公开(公告)号:US20240354886A1
公开(公告)日:2024-10-24
申请号:US18599418
申请日:2024-03-08
Applicant: Intel Corporation
Inventor: Sreenivas Kothandaraman , Karthik Vaidyanathan , Abhishek R. Appu , Karol Szerszen , Prasoonkumar Surti
IPC: G06T1/20 , G06F9/38 , G06F16/907 , G06T7/90
CPC classification number: G06T1/20 , G06F9/3838 , G06F9/3877 , G06F16/907 , G06T7/90
Abstract: An apparatus to facilitate compression of memory data is disclosed. The apparatus comprises one or more processors to receive uncompressed data, adapt a format of the uncompressed data to a compression format, perform a color transformation from a first color space to a second color space, perform a residual computation to generate residual data, compress the residual data via entropy encoding to generate compressed data and packing the compressed data.
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公开(公告)号:US20240282042A1
公开(公告)日:2024-08-22
申请号:US18587761
申请日:2024-02-26
Applicant: Intel Corporation
Inventor: Karthik Vaidyanathan , Abhishek Appu , Vasanth Ranganathan , Joydeep Ray , Prasoonkumar Surti
CPC classification number: G06T15/005 , G06T15/06
Abstract: Apparatus and method for stack throttling. For example, one embodiment of an apparatus comprises: execution circuitry comprising a plurality of functional units to execute a plurality of ray shaders and generate a plurality of primary rays and a corresponding plurality of ray messages; a first in first out (FIFO) buffer to queue the ray messages generated by the EUs; a cache to store one or more of the plurality of primary rays; a memory-backed stack to store a first subset of the plurality of ray messages in a corresponding plurality of entries; memory-backed stack management circuitry to either store a second subset of the plurality of ray messages to the memory-backed stack, or to temporarily store the one or more the second subset of the plurality of ray messages to a memory subsystem based, at least in part, on a number of entries currently occupied by ray messages in the memory-backed stack; and ray traversal circuitry to read a next ray message from the memory-backed stack, retrieve a next primary ray identified by the ray message from the cache or a memory subsystem, and perform traversal operations on the next primary ray.
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公开(公告)号:US20240257294A1
公开(公告)日:2024-08-01
申请号:US18436494
申请日:2024-02-08
Applicant: Intel Corporation
Inventor: Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L. Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
CPC classification number: G06T1/20 , G06F9/45533 , G06F9/5061 , G06F9/5094 , G06N3/044 , G06N3/045 , G06N3/063 , G06N3/084 , G06F8/41 , G06F2009/45583
Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.
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公开(公告)号:US20240169664A1
公开(公告)日:2024-05-23
申请号:US18535367
申请日:2023-12-11
Applicant: Intel Corporation
Inventor: Karthik Vaidyanathan , Marco Salvi , Robert M. Toth
CPC classification number: G06T15/503 , G06T1/20 , G06T2200/12
Abstract: In some embodiments, a given frame or picture may have different shading rates. In one embodiment in some areas of the frame or picture the shading rate may be less than once per pixel and in other places it may be once per pixel. Examples where the shading rate may be reduced include areas where there is motion and camera defocus, areas of peripheral blur, and in general, any case where the visibility is reduced anyway. The shading rate may be changed in a region, such as a shading quad, by changing the size of the region.
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