公开(公告)号：US10985264B2

公开(公告)日：2021-04-20

申请号：US16378584

申请日：2019-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Hung Chen ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Chia-Jung Hsu ,  Yu-Hsiang Lin

IPC: H01L27/108 ,  H01L21/20 ,  H01L29/66 ,  H01L21/308 ,  H01L29/78 ,  H01L27/088 ,  H01L27/06 ,  H01L21/033 ,  H01L27/12

Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.

公开(公告)号：US10985048B2

公开(公告)日：2021-04-20

申请号：US16732367

申请日：2020-01-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer on the first gate structure; removing the first gate structure to form a first recess; and forming a dielectric layer in the first recess.

公开(公告)号：US10347526B1

公开(公告)日：2019-07-09

申请号：US15951683

申请日：2018-04-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/532

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a gate structure, and a conductive element. The gate structure is on the substrate. The gate structure includes a gate electrode and a cap layer on the gate electrode. The conductive element is adjoined with an outer surface of the gate structure. The conductive element includes a lower conductive portion and an upper conductive portion electrically connected on the lower conductive portion and adjoined with the cap layer. The lower conductive portion and the upper conductive portion have an interface therebetween. The interface is below an upper surface of the cap layer.

公开(公告)号：US20190172752A1

公开(公告)日：2019-06-06

申请号：US15830008

申请日：2017-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chi-Ting Wu ,  Yu-Hsiang Lin

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/768 ,  H01L23/535 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/823475 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823468 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure and a second gate structure on a substrate and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure into a first metal gate and the second gate structure into a second metal gate; removing part of the ILD layer between the first metal gate and the second metal gate to form a recess; forming a first spacer and a second spacer in the a recess; performing a first etching process to form a first contact hole; and performing a second etching process to extend the first contact hole into a second contact hole.

公开(公告)号：US20150279957A1

公开(公告)日：2015-10-01

申请号：US14230223

申请日：2014-03-31

Applicant: United Microelectronics Corp.

Inventor： Yu-Ping Wang ,  Jyh-Shyang Jenq ,  Yu-Hsiang Lin ,  Hsuan-Hsu Chen ,  Chien-Hao Chen ,  Yi-Han Ye

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.

Abstract translation: 公开了一种半导体结构及其制造方法。 半导体结构包括第一栅极结构，第二栅极结构和第二电介质间隔物。 彼此相邻的第一栅极结构和第二栅极结构中的每一个包括第一电介质间隔物。 第二电介质间隔物位于第一栅极结构的相对侧壁中的一个上，而不设置在第二栅极结构的电介质间隔物上。