公开(公告)号：US11195918B1

公开(公告)日：2021-12-07

申请号：US17026062

申请日：2020-09-18

Applicant: United Microelectronics Corp.

Inventor： Chia-Jung Hsu ,  Chin-Hung Chen ,  Chun-Ya Chiu ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Tsai-Yu Wen ,  Shi You Liu ,  Yu-Hsiang Lin

IPC: H01L29/10 ,  H01L21/265 ,  H01L29/167 ,  H01L29/06

Abstract: A structure of semiconductor device is provided, including a substrate. A first trench isolation and a second trench isolation are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the germanium doped layer region.

公开(公告)号：US10971397B2

公开(公告)日：2021-04-06

申请号：US16569544

申请日：2019-09-12

Applicant: United Microelectronics Corp.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chia-Jung Hsu ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L21/768 ,  H01L27/108

Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate is provided. The substrate includes a pixel region having a first conductive region and a logic region having a second conductive region. A dielectric layer is formed on the substrate to cover the first conductive region. A first contact opening is formed in the dielectric layer to expose the first conductive region. A doped polysilicon layer is sequentially formed in the first contact opening. A first metal silicide layer is formed on the doped polysilicon layer. A second contact opening is formed in the dielectric layer to expose the second conductive region. A barrier layer and a metal layer are respectively formed in the first contact opening and the second contact opening.

公开(公告)号：US20210050456A1

公开(公告)日：2021-02-18

申请号：US16572556

申请日：2019-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Hung Chen ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Chun-Ya Chiu ,  Chia-Jung Hsu ,  Yu-Hsiang Lin

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.

公开(公告)号：US10546922B2

公开(公告)日：2020-01-28

申请号：US15890320

申请日：2018-02-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq ,  Tsung-Mu Yang

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L23/535 ,  H01L21/768 ,  H01L23/485 ,  H01L29/08 ,  H01L29/417 ,  H01L21/285

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.

公开(公告)号：US10529825B2

公开(公告)日：2020-01-07

申请号：US15951147

申请日：2018-04-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chi-Ting Wu ,  Yu-Hsiang Lin

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source/drain region, a source/drain contact structure, a first dielectric layer, a first spacer, and a first connection structure. The gate structure is disposed on the semiconductor substrate. The source/drain region is disposed in the semiconductor substrate and disposed at a side of the gate structure. The source/drain contact structure is disposed on the source/drain region. The first dielectric layer is disposed on the source/drain contact structure and the gate structure. The first spacer is disposed in a first contact hole penetrating the first dielectric layer on the source/drain contact structure. The first connection structure is disposed in the first contact hole. The first connection structure is surrounded by the first spacer in the first contact hole, and the first connection structure is connected with the source/drain contact structure.

公开(公告)号：US20190221469A1

公开(公告)日：2019-07-18

申请号：US15873838

申请日：2018-01-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/785

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer on the first gate structure; removing the first gate structure to form a first recess; and forming a dielectric layer in the first recess.

公开(公告)号：US10256146B2

公开(公告)日：2019-04-09

申请号：US15871037

申请日：2018-01-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chao-Hung Lin ,  Chih-Kai Hsu ,  Jyh-Shyang Jenq

IPC: H01L21/76 ,  H01L23/535 ,  H01L27/11 ,  H01L21/768 ,  H01L21/033 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a first and second fin shaped structures, a first and second gate structures and a first and second plugs. The first and second fin shaped structures are disposed on a first region and a second region of a substrate and the first and second gate structure are disposed across the first and second fin shaped structures, respectively. A dielectric layer is disposed on the substrate, covering the first and second gate structure. The first and second plugs are disposed in the dielectric layer, wherein the first plug is electrically connected first source/drain regions adjacent to the first gate structure and contacts sidewalls of the first gate structure, and the second plug is electrically connected to second source/drain regions adjacent to the second gate structure and not contacting sidewalls of the second gate structure.

公开(公告)号：US10249488B1

公开(公告)日：2019-04-02

申请号：US15866489

申请日：2018-01-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chi-Ting Wu ,  Yu-Hsiang Lin

IPC: H01L21/02 ,  H01L21/67 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L27/088 ,  H01L29/165

Abstract: A semiconductor device with three transistors of same conductive type but different threshold voltage is provided in the present invention, wherein the first transistor includes a high-k dielectric layer, a first bottom barrier metal layer, a second bottom barrier metal layer, a work function metal layer and a low resistance metal. The second transistor includes the high-k dielectric layer, the first bottom barrier metal layer, the second bottom barrier metal layer and the low resistance metal, and a third transistor on the substrate. The third transistor includes the high-k dielectric layer, the first bottom barrier metal layer and the low resistance metal.

公开(公告)号：US10236383B2

公开(公告)日：2019-03-19

申请号：US15916261

申请日：2018-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Jyh-Shyang Jenq

IPC: H01L29/04 ,  H01L29/78 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first fin-shaped structure thereon; forming a spacer adjacent to the first fin-shaped structure; using the spacer as mask to remove part of the substrate for forming a second fin-shaped structure, wherein the second fin-shaped structure comprises a top portion and a bottom portion; and forming a doped portion in the bottom portion of the second fin-shaped structure.

公开(公告)号：US10141432B2

公开(公告)日：2018-11-27

申请号：US15695019

申请日：2017-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L21/3105 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method for making a semiconductor device. A substrate having a fin structure is provided. A continuous dummy gate line is formed on the substrate. The dummy gate line strides across the fin structure. A source/drain structure is formed on the fin structure on both sides of the dummy gate line. An interlayer dielectric (ILD) is formed on the dummy gate line and around the dummy gate line. The ILD is polished to reveal a top surface of the dummy gate line. After polishing the ILD, the dummy gate line is segmented into separate dummy gates.