公开(公告)号：US20060007636A1

公开(公告)日：2006-01-12

申请号：US11226565

申请日：2005-09-14

Applicant: Thomas Smyth ,  Michelle Nelson ,  Sarah Mobley ,  Charles Newton

Inventor： Thomas Smyth ,  Michelle Nelson ,  Sarah Mobley ,  Charles Newton

IPC: H01G4/228

CPC classification number: H01L23/49822 ,  H01L23/642 ,  H01L2224/32225 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/162 ,  H05K3/4626 ,  H05K3/4629 ,  H05K3/4688 ,  H05K2201/0195 ,  H05K2201/09672 ,  Y10T29/4913

Abstract: A method for making an electronic module includes forming a low temperature co-fired ceramic (LTCC) substrate with at least one capacitive structure embedded therein. Forming the LTCC substrate may include arranging first and second unsintered ceramic layers and the at least one capacitive structure therebetween. The at least one capacitive structure may include a pair of electrode layers, an inner dielectric layer between the pair of electrode layers, and at least one outer dielectric layer adjacent at least one of the electrode layers and opposite the inner dielectric layer. The at least one outer dielectric layer preferably has a dielectric constant less than a dielectric constant of the inner dielectric layer. The unsintered ceramic layers and the at least one capacitive structure may also be heated, and at least one electronic device may be mounted on the LTCC substrate and electrically connected to the at least one embedded capacitive structure.

公开(公告)号：US06946926B2

公开(公告)日：2005-09-20

申请号：US10469032

申请日：2003-02-19

Applicant: Mikihiro Shimada ,  Kaoru Ishida ,  Hiroyuki Asakura

Inventor： Mikihiro Shimada ,  Kaoru Ishida ,  Hiroyuki Asakura

IPC: H05K3/46 ,  H01B11/00 ,  H01P3/00 ,  H01P3/02 ,  H01P3/08 ,  H04B3/32 ,  H05K1/00 ,  H05K1/02 ,  H01P3/04

CPC classification number: H01P3/026 ,  H01P3/023 ,  H05K1/0228 ,  H05K1/0237 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/09672

Abstract: A wired transmission path includes first and second differential transmission paths. The first differential transmission path is composed of two strip lines, and the second differential transmission path is composed of two strip lines. Each of the strip lines of the first differential transmission path is disposed at an equal distance from the strip lines of the second differential transmission path. Thus, there is provided a wired transmission path including a plurality of differential transmission paths in such a manner so as to cancel crosstalk.

Abstract translation: 有线传输路径包括第一和第二差分传输路径。 第一差分传输路径由两条带状线组成，第二差分传输路径由两条带状线组成。 第一差分传输路径的每条带状线设置在与第二差分传输路径的带状线相等的距离处。 因此，提供了一种包括多个差分传输路径的有线传输路径，以便消除串扰。

公开(公告)号：US20050136747A1

公开(公告)日：2005-06-23

申请号：US11014097

申请日：2004-12-15

Applicant: Jack Caveney ,  Scott Lesniak

Inventor： Jack Caveney ,  Scott Lesniak

IPC: H01R13/66 ,  H01R24/00 ,  H05K1/02 ,  H05K1/16

CPC classification number: H01R4/2416 ,  H01R4/2433 ,  H01R13/6466 ,  H01R13/6469 ,  H01R13/665 ,  H01R13/6658 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/10189 ,  Y10S439/941 ,  Y10S439/942 ,  Y10T29/49201 ,  Y10T29/49202 ,  Y10T29/49204 ,  Y10T29/49208

Abstract: A network cable jack includes a printed circuit board (PCB) for balancing both inductive and capacitive coupling. Using a PCB allows compact trace paths to be formed without significantly increasing manufacturing costs. By including on each trace path two distinct inductance zones separated by a neutral zone, significant gains in degrees of freedom are achieved for designing PCB trace patterns in which a pair of inductive coupling zones jointly offset the inductive coupling caused by a specification plug and the jack contacts, both in magnitude and phase angle. Further, using distinct inductance zones offers more freedom regarding the placement of capacitive plates for use in capacitance balancing as well as the placement of terminals and insulation displacement contacts. Although the magnitude of a capacitive coupling is determined by the length of the capacitor plates parallel to current carrying traces, the approach allows capacitive and inductive coupling to be balanced independently.

Abstract translation: 网络电缆插孔包括用于平衡电感和电容耦合的印刷电路板（PCB）。 使用PCB可以形成紧凑的轨迹路径，而不会显着增加制造成本。 通过在每个迹线路径上包括两个由中性区域分开的不同的电感区域，实现了自由度的显着增益，用于设计PCB迹线图案，其中一对感应耦合区域共同抵消了由规格插头和插孔引起的感性耦合 触点，幅度和相位角。 此外，使用不同的电感区域可以提供更多的自由度，用于电容平板的放置以及端子和绝缘位移触点的放置。 虽然电容耦合的大小由与载流轨迹平行的电容器板的长度确定，但该方法允许电容和电感耦合独立平衡。

公开(公告)号：US20050133257A1

公开(公告)日：2005-06-23

申请号：US10740398

申请日：2003-12-22

Applicant: John Lauffer ,  Voya Markovich ,  James McNamara ,  David Thomas

Inventor： John Lauffer ,  Voya Markovich ,  James McNamara ,  David Thomas

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/11 ,  H05K3/42

CPC classification number: H05K1/0216 ,  H05K1/0228 ,  H05K2201/09236 ,  H05K2201/09672 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A printed circuit board and a method of making same in which the board includes a common power plane having dielectric layers on opposing sides thereof and a signal layer on each of said dielectric layers, each signal layer comprising a plurality of substantially parallel signal lines running in substantially similar directions across said signal layers. Predetermined portions of the signal lines in one signal layer are aligned relative to and also parallel to corresponding signal lines in the other signal layer, with the power plane being located between these portions. Through hole connections are provided between selected signal lines in the two layers, these occurring through clearance holes in the power plane so as to be isolated therefrom.

Abstract translation: 一种印刷电路板及其制造方法，其中所述板包括在其相对侧上具有电介质层的公共电源平面和每个所述电介质层上的信号层，每个信号层包括多条基本上平行的信号线， 基本相似的方向跨越所述信号层。 一个信号层中的信号线的预定部分相对于并且平行于另一个信号层中的相应的信号线，而功率平面位于这些部分之间。 在两层中的选定信号线之间提供通孔连接，这些连接通过电源平面中的间隙而发生，从而与其隔离。

公开(公告)号：US06888427B2

公开(公告)日：2005-05-03

申请号：US10365262

申请日：2003-02-11

Applicant: Roger Sinsheimer ,  Vladan Temer

Inventor： Roger Sinsheimer ,  Vladan Temer

IPC: H01P3/08 ,  H05K1/00 ,  H05K1/02

CPC classification number: H01P3/081 ,  H01P3/084 ,  H05K1/024 ,  H05K1/0393 ,  H05K2201/0116 ,  H05K2201/0715 ,  H05K2201/09672 ,  H05K2201/2036

Abstract: A transmission line circuit is described which includes a conductive plane, a plurality of signal traces, and an intermediate layer between the conductive plane and the signal traces. The intermediate layer maintains a substantially constant separation between the conductive plane and the signal traces. At least a portion of the intermediate layer comprises air. The signal traces and the conductive plane form transmission lines.

Abstract translation: 描述了传输线电路，其包括导电平面，多个信号迹线以及导电平面和信号迹线之间的中间层。 中间层在导电平面和信号迹线之间保持基本恒定的间隔。 中间层的至少一部分包括空气。 信号迹线和导电平面形成传输线。

公开(公告)号：US20050003199A1

公开(公告)日：2005-01-06

申请号：US10745587

申请日：2003-12-29

Applicant: Minoru Takaya ,  Toshikazu Endo ,  Kenichi Kawabata

Inventor： Minoru Takaya ,  Toshikazu Endo ,  Kenichi Kawabata

IPC: B32B15/08 ,  C08G59/42 ,  C08J5/24 ,  C08L63/00 ,  C08L67/03 ,  H01F17/00 ,  H01F27/32 ,  H01L23/498 ,  H01L25/16 ,  H05K1/00 ,  H05K1/03 ,  H05K1/16 ,  H05K3/46 ,  B32B27/38 ,  B32B27/04

CPC classification number: B32B15/08 ,  B32B9/005 ,  B32B27/08 ,  B32B2305/076 ,  B32B2305/08 ,  B32B2307/202 ,  B32B2307/204 ,  B32B2307/206 ,  C08G59/4223 ,  C08J5/10 ,  C08J5/18 ,  C08J5/24 ,  C08J2363/00 ,  C08L63/00 ,  C08L67/03 ,  H01F17/0006 ,  H01F27/323 ,  H01F27/327 ,  H01F2017/048 ,  H01L23/49894 ,  H01L24/48 ,  H01L25/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0373 ,  H05K1/162 ,  H05K3/4626 ,  H05K3/4676 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2201/09672 ,  Y10T428/2971 ,  Y10T428/31511 ,  Y10T428/31515 ,  Y10T428/31522 ,  Y10T428/31529 ,  C08L2666/18 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention provides electronic parts which comprise a composite dielectric layer composed of an organic insulating material and a dielectric ceramic powder having a larger relative dielectric constant than the organic insulating material, and which also comprise conductive element sections forming inductor elements, etc., wherein the organic insulating material comprises a cured resin obtained by curing reaction of an epoxy resin with an active ester compound obtained by reaction between a compound with two or more carboxyl groups and a compound with a phenolic hydroxyl group. The dielectric ceramic powders of the described electronic parts have larger relative dielectric constants than the organic insulating materials, and the organic insulating materials have low dielectric loss tangents. It is possible to adequately reduce time-dependent dielectric constant changes in the high-frequency range of 100 MHz and above even with prolonged use at high temperatures of 100° C. and higher, while it is also possible to satisfactorily prevent deformation and other damage to the electronic parts during their handling.

Abstract translation: 本发明提供的电子部件包括由有机绝缘材料构成的复合电介质层和具有比有机绝缘材料更大的相对介电常数的介电陶瓷粉末，并且还包括形成电感元件的导电元件等，其中， 有机绝缘材料包括通过使环氧树脂与通过具有两个或更多个羧基的化合物和具有酚羟基的化合物之间的反应获得的活性酯化合物的反应固化而获得的固化树脂。 所述电子部件的介电陶瓷粉末具有比有机绝缘材料更大的相对介电常数，有机绝缘材料具有低的介电损耗角正切。 即使长时间在100℃以上的高温下使用也可以充分降低100MHz以上的高频范围的时间依赖介电常数的变化，同时也可以令人满意地防止变形等损伤 在处理电子零件时。

公开(公告)号：US06828506B2

公开(公告)日：2004-12-07

申请号：US10445037

申请日：2003-05-27

Applicant: Yoshinori Murakami

Inventor： Yoshinori Murakami

IPC: H01B708

CPC classification number: H05K1/0216 ,  H01L23/5383 ,  H01L25/072 ,  H01L2924/0002 ,  H05K2201/09672 ,  H05K2201/09727 ,  H01L2924/00

Abstract: A wiring or electrode structure is configured to reduce the wiring inductance of the power conductors in a semiconductor power module and prevent as much as possible the emission of interference electromagnetic waves. The wiring or electrode structure has an insulation layer that faces a main surface of a conductive base layer, a first conductor that faces the surface of the insulation layer, and a second conductor through which current flows in the opposite direction as the current that flows in the first conductor. The second electrical conductor overlying the first electrical conductor such opposite longitudinal edges of the second electrical conductor extend beyond corresponding longitudinal edges of the first electrical conductor at all locations by predetermined distances.

Abstract translation: 布线或电极结构被配置为减少半导体功率模块中的电力导体的布线电感，并尽可能地防止干扰电磁波的发射。 布线或电极结构具有面向导电基底层的主表面的绝缘层，面向绝缘层的表面的第一导体和电流沿相反方向流动的第二导体，作为流过电流的电流 第一个指挥。 覆盖第一电导体的第二电导体，第二电导体的相对纵向边缘延伸超过所有位置处第一电导体的相应纵向边缘预定距离。

公开(公告)号：US06813138B1

公开(公告)日：2004-11-02

申请号：US10427230

申请日：2003-04-30

Applicant: Wei-Ming Jow ,  Pei-Shen Wei ,  Ching-Liang Weng ,  Chun-Kun Wu ,  Chang-Sheng Chen

Inventor： Wei-Ming Jow ,  Pei-Shen Wei ,  Ching-Liang Weng ,  Chun-Kun Wu ,  Chang-Sheng Chen

IPC: H01G4228

CPC classification number: H01G4/232 ,  H05K1/162 ,  H05K3/429 ,  H05K2201/09672 ,  H05K2201/09718

Abstract: An embedded microelectronic capacitor equipped with geometrically-centered electrodes which includes an upper electrode plate of a first polarity; a middle electrode plate of a second polarity opposite to the first polarity; at least one lower electrode plate of the first polarity in electrical communication with the upper electrode plate through a center via. The center via is positioned at a distance from a geometric center of the middle electrode plate of not larger than 50% of the diameter of the plate, and preferably not larger than 30% of the diameter.

Abstract translation: 一种配备有几何中心电极的嵌入式微电子电容器，其包括第一极性的上电极板; 与第一极性相反的第二极性的中间电极板; 至少一个第一极性的下电极板通过中心通孔与上电极板电连通。 中心通孔位于中间电极板的几何中心一定距离处，不大于板的直径的50％，优选不大于直径的30％。

公开(公告)号：US20040132229A1

公开(公告)日：2004-07-08

申请号：US10738799

申请日：2003-12-17

Inventor： Jean Audet ,  Timothy W. Budell ,  Patrick H. Buffet ,  Alain Caron

IPC: H01L021/44

CPC classification number: H05K1/0216 ,  G06F17/5077 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/0298 ,  H05K3/0005 ,  H05K2201/09236 ,  H05K2201/09672 ,  H01L2924/00

Abstract: The present invention relates to a method for optimization of a signal wire structure, providing concurrent optimization of a plurality of wire parameters, providing a plurality of wiring solutions, wherein each of said wiring solutions produces a wiring package having different wire parameters, providing an electronic package, determining the optimal wiring solutions for said electronic package; and producing an electronic package, using the optimized wiring package solutions. The resulting apparatus is also disclosed.

Abstract translation: 本发明涉及一种优化信号线结构的方法，提供多个线参数的并发优化，提供多个布线解决方案，其中每个所述布线方案产生具有不同导线参数的布线包，提供电子 确定所述电子封装的最佳布线方案; 并使用优化的布线包解决方案生产电子封装。 还公开了所得装置。

公开(公告)号：US20040085149A1

公开(公告)日：2004-05-06

申请号：US10469032

申请日：2003-08-26

Inventor： Mikihiro Shimada ,  Kaoru Ishida ,  Hiroyuki Asakura

IPC: H01P003/02

CPC classification number: H01P3/026 ,  H01P3/023 ,  H05K1/0228 ,  H05K1/0237 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/09672

Abstract: A wired transmission path 1 includes first and second differential transmission paths 12 and 13. The first differential transmission path 12 is composed of two strip lines 121 and 122, and the second differential transmission path 13 is composed of two strip lines 131 and 132. Each of the strip lines 121 and 122 is disposed at an equal distance from the strip lines 131 and 132. Thus, there is provided a wired transmission path including a plurality of differential transmission paths in such a manner as to cancel crosstalk.

Abstract translation: 有线传输路径1包括第一和第二差分传输路径12和13.第一差分传输路径12由两条带状线121和122组成，第二差分传输路径13由两条带状线131和132组成。每条 带状线121和122被设置在与带状线131和132相等的距离处。因此，提供一种包括多个差分传输路径的有线传输路径，以消除串扰。