公开(公告)号：US20170154951A1

公开(公告)日：2017-06-01

申请号：US14955882

申请日：2015-12-01

Applicant: Altera Corporation

Inventor： Yan Cui ,  Queennie Suan Imm Lim ,  Shuxian Chen

IPC: H01L49/02 ,  H01L23/552 ,  H01L21/66 ,  H01L27/08

CPC classification number: H01L28/88 ,  H01L23/552

Abstract: In one embodiment, a capacitor structure includes a substrate, a dielectric stack, a first conductor segment, a second conductor segment and a shielding conductor segment. The dielectric stack is formed on the substrate. A first layer of the dielectric stack includes a plurality of conductor segments routed only in a first direction. A first conductor segment among the multiple conductor segments may be biased to a first voltage. The second conductor segment among the multiple conductor segments may be biased to a second voltage. The shielding conductor segment may be biased to the second voltage and is formed at an end of the first conductor segment. In addition to that, the capacitances for the capacitor structure may be adjusted while the footprint of the capacitor structure is fixed.

公开(公告)号：US09665670B1

公开(公告)日：2017-05-30

申请号：US13931069

申请日：2013-06-28

Applicant: Altera Corporation

Inventor： Bruce B. Pedersen

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5022 ,  G06F9/45508

Abstract: Integrated circuits may include synchronous nodes and asynchronous routing elements coupled between the synchronous nodes. A synchronous design implemented in such an integrated circuit may identify a register chain having a source register, a destination register, and intermediate registers. A virtual register may be created for each of the intermediate registers, which may then be removed from the synchronous design. The created virtual registers may be connected in series to form a virtual register chain between the source and destination registers. Each of the created virtual registers may be assigned to an asynchronous routing element that connects the source and destination registers on the integrated circuit. EDA tools such as viewers or a timing analysis tool may be configured to display the virtual registers instead of the asynchronous interconnection elements.

公开(公告)号：US09660846B2

公开(公告)日：2017-05-23

申请号：US14633080

申请日：2015-02-26

Applicant: Altera Corporation

Inventor： Weiqi Ding ,  Mengchi Lui ,  Wilson Wong ,  Sergey Y. Shumarayev

IPC: H04L25/03 ,  H04L7/00

CPC classification number: H04L25/03885 ,  H04L7/0054 ,  H04L25/03019 ,  H04L25/03878

Abstract: Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gpbs and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

公开(公告)号：US09658830B1

公开(公告)日：2017-05-23

申请号：US14320499

申请日：2014-06-30

Applicant: Altera Corporation

Inventor： Ketan Padalia ,  David Cashman ,  David Lewis ,  Andy L. Lee ,  Jay Schleicher ,  Jinyong Yuan ,  Henry Kim

IPC: G06F7/575 ,  H03K19/177

CPC classification number: G06F7/575 ,  H03K19/177 ,  H03K19/17728

Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT. An output line network includes a network of output lines, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture. The described LUT's can perform arithmetic efficiently, as well as non-arithmetic functions.

公开(公告)号：US09647663B1

公开(公告)日：2017-05-09

申请号：US15193518

申请日：2016-06-27

Applicant: Altera Corporation

Inventor： Hoong Chin Ng

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/018 ,  H03K19/00 ,  H03K19/177

CPC classification number: H03K19/0005 ,  H03K19/01825 ,  H03K19/018564 ,  H03K19/17744

Abstract: An input buffer circuit that receives differential signals includes a first resistive path circuit, a second resistive path circuit and a feedback circuit. The first resistive path circuit may generate a first common mode voltage from the differential signals. The feedback circuit is coupled to the first resistive path circuit. The feedback circuit receives the first common mode voltage as an input. The second resistive path circuit includes a transistor circuit and a resistor formed in a serial circuit configuration. The second resistive path circuit may generate a second common mode voltage on a node formed between the transistor circuit and the resistor by controlling activation of the transistor circuit using outputs from the feedback circuit. The first common mode voltage may be substantially identical to the second common mode voltage.

公开(公告)号：US20170117250A1

公开(公告)日：2017-04-27

申请号：US14923187

申请日：2015-10-26

Applicant: Altera Corporation

Inventor： Yuanlin Xie

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517

Abstract: An integrated circuit package may include a first integrated circuit die having a first bump structure, a second integrated circuit die having a second bump structure, and a detachable interconnect structure having first and second conductive structures that is positioned between the first and second integrated circuit dies. In order to establish electrical communication between the first and second integrated circuit dies, the first conductive structure of the detachable interconnect structure is connected to the first bump structure of the first integrated circuit die, and the second conductive structure of the detachable interconnect structure is connected to the second bump structure of the second integrated circuit die. The detachable interconnect structure may also be used to facilitate wafer-level testing prior to packaging the first and second integrated circuit dies to form the integrated circuit package.

公开(公告)号：US09633158B1

公开(公告)日：2017-04-25

申请号：US14538784

申请日：2014-11-11

Applicant: ALTERA CORPORATION

Inventor： Jakob Raymond Jones ,  Prasanna Padmanabhan

IPC: H01L27/118 ,  G06F17/50 ,  H01L27/02 ,  G06F15/80 ,  H01L27/115 ,  H01L23/528

CPC classification number: G06F17/5068 ,  G06F15/8015 ,  G06F17/50 ,  G06F17/5054 ,  G06F2217/66 ,  H01L23/528 ,  H01L27/115 ,  H01L27/118 ,  H01L27/11807 ,  H03K19/17728

Abstract: Systems and methods for reconfiguration of a hardened intellectual property (IP) block in an integrated circuit (IC) device are provided. Reconfiguration of the hardened IP block in the IC device may transition between functions supported by the hardened IP block. A transition may occur as a pre-configured profile is selected to reconfigure the hardened IP block. Further, configuration data associated with each of the pre-configured profiles of the hardened IP block may be generated and storage space to store the configuration data may be created. Additionally, reconfiguration control logic to read and implement the configuration data in hard IP design primitives may also be generated.

公开(公告)号：US20170103298A1

公开(公告)日：2017-04-13

申请号：US14879928

申请日：2015-10-09

Applicant: Altera Corporation

Inventor： Andrew Chaang Ling ,  Gordon Raymond Chiu ,  Utku Aydonat

IPC: G06N3/04

CPC classification number: G06N3/063 ,  G06N3/0454

Abstract: A method for implementing a convolutional neural network (CNN) accelerator on a target includes identifying characteristics and parameters for the CNN accelerator. Resources on the target are identified. A design for the CNN accelerator is generated in response to the characteristics and parameters of the CNN accelerator and the resources on the target.

公开(公告)号：US09621467B1

公开(公告)日：2017-04-11

申请号：US14470729

申请日：2014-08-27

Applicant: ALTERA CORPORATION

Inventor： Jaewon Seo

IPC: H04L12/803 ,  H04L12/801

CPC classification number: H04L47/125 ,  H04L47/39

Abstract: One embodiment relates to a data transmission circuit with deterministic flow control that includes a plurality of FIFO buffers, a plurality of transmitter lanes, a transmitter MAC circuit, and a transmitter aligner circuit. The transmitter aligner circuit includes control circuitry that performs one or more iterations of a procedure to optimize a starting offset, where the starting offset provides an initial delay between the writing of the data bits to the plurality of FIFO buffers and the reading of the data bits from the plurality of FIFO buffers. Another embodiment relates to a method of reducing data path latency in a data transmission circuit with deterministic flow control. Other embodiments, aspects, and features of the invention are also disclosed.

公开(公告)号：US09619423B1

公开(公告)日：2017-04-11

申请号：US14066447

申请日：2013-10-29

Applicant: ALTERA CORPORATION

Inventor： Steven Perry

IPC: G06F12/00 ,  G06F13/40 ,  G06F12/06 ,  G06F12/0831

CPC classification number: G06F13/404 ,  G06F12/0833

Abstract: Systems and devices are provided for broadcasting a message to addressed logic blocks in lieu of, or in addition to, programming individual status registers of an integrated circuit. One such device may be an integrated circuit that includes a broadcast bus and addressed logic blocks. The broadcast bus may broadcast an addressed message that includes content and a target address. Each of the addressed logic blocks may receive the addressed message from the broadcast bus and use the content of the addressed message only when the target address matches an address assigned to that logic block.