公开(公告)号：US11658084B2

公开(公告)日：2023-05-23

申请号：US17318066

申请日：2021-05-12

Applicant: Powertech Technology Inc.

Inventor： Shun-Ming Yu ,  Han-Ming Chu

IPC: H01L23/31 ,  H01L21/56

CPC classification number: H01L23/3121 ,  H01L21/565

Abstract: A semiconductor packaging structure includes a substrate, a wiring layer, a mask layer, and a sealing layer. The substrate has an effective region and a dummy region surrounding the effective region. The wiring layer is disposed on the effective and dummy regions, and is formed with a predetermined pattern including spaced-apart protrusions to define at least one cavity partially exposing the dummy region. The mask layer covers the wiring layer, and is formed with a through hole to communicate in space with the cavity. The through hole is smaller in size than the cavity, and cooperates with the cavity to form an accommodating space. The sealing layer covers the mask layer, and includes an engaging element filling the accommodating space and adhering to the substrate.

公开(公告)号：US11557533B2

公开(公告)日：2023-01-17

申请号：US17080853

申请日：2020-10-27

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/24 ,  H01L21/78 ,  H01L23/16 ,  H01L23/367 ,  H01L23/552

Abstract: A package structure including a redistribution circuit structure, a first chip, a second chip, a first circuit board, a second circuit board, and a plurality of conductive terminals is provided. The redistribution circuit structure has a first connection surface and a second connection surface opposite to the first connection surface. The first chip and the second chip are disposed on the first connection surface and are electrically connected to the redistribution circuit structure. The first circuit board and the second circuit board are disposed on the second connection surface and are electrically connected to the redistribution circuit structure. The conductive terminals are disposed on the first circuit board or the second circuit board. The conductive terminals are electrically connected to the first circuit board or the second circuit board. A manufacturing method of a package structure is also provided.

公开(公告)号：US11456243B2

公开(公告)日：2022-09-27

申请号：US17080859

申请日：2020-10-27

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L23/24 ,  H01L21/78 ,  H01L23/16 ,  H01L23/367 ,  H01L23/552

Abstract: A semiconductor package structure, including a circuit substrate, at least two chips, an encapsulant, and a redistribution layer, is provided. The circuit substrate has a first surface and a second surface opposite to the first surface. The at least two chips are disposed on the first surface. Each of the at least two chips has an active surface facing the circuit substrate and includes multiple first conductive connectors and multiple second conductive connectors disposed on the active surface. A pitch of the first conductive connectors is less than a pitch of the second conductive connectors. The encapsulant encapsulates the at least two chips. The redistribution layer is located on the second surface. The first conductive connectors are electrically connected to the redistribution layer by the circuit substrate. The second conductive connectors are electrically connected to the circuit substrate. A manufacturing method of a semiconductor package structure is also provided.

公开(公告)号：US20220165709A1

公开(公告)日：2022-05-26

申请号：US17210452

申请日：2021-03-23

Applicant: Powertech Technology Inc.

Inventor： Yin-Huang KUNG ,  Chia-Hung LIN ,  Fu-Yuan YAO ,  Chun-Wu LIU

IPC: H01L25/065 ,  H01L25/00

Abstract: A stacked semiconductor package has a substrate, a first chip, at least one spacer, a second chip and an encapsulation. The first chip and the second chip are intersecting stacked on the substrate. The at least one spacer is stacked on the substrate to support the second chip. The encapsulation is formed to encapsulate the substrate, the first chip, the at least one spacer and the second chip. The at least one spacer is made of the material of the encapsulation. Therefore, the adhesion between the at least one spacer and the encapsulation is enhanced to avoid the delamination during the reliability test and enhances the reliability of the stacked semiconductor package.

公开(公告)号：US20220148955A1

公开(公告)日：2022-05-12

申请号：US17198653

申请日：2021-03-11

Applicant: Powertech Technology Inc.

Inventor： Chih-Yen SU ,  Chun-Te Lin

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package has a substrate, a chip and an encapsulation. The substrate has a dielectric layer, a copper wiring layer and a solder resist layer formed thereon. The copper wiring layer is formed on the dielectric layer and is covered by the solder resist layer. The solder resist layer has a chip area defined thereon and an annular opening formed thereon. The annular opening surrounds the chip area and exposes part of the copper wiring layer. The chip is mounted on the chip area and is encapsulated by the encapsulation. Therefore, the semiconductor package with the annular opening makes the solder resist layer discontinuous, and the concentration stress is decreased to avoid a crack formed on the solder resist layer or the copper wiring layer when doing thermal-cycle test.

公开(公告)号：US20220118631A1

公开(公告)日：2022-04-21

申请号：US17183752

申请日：2021-02-24

Applicant: Powertech Technology Inc.

Inventor： Wu-Yi CHOU ,  Kun-Chi HSU ,  Chin-Ta WU ,  Yung-Chin SHIH ,  Chin Cheng LIU ,  Jentung TSENG

IPC: B25J15/06 ,  H01L21/683

Abstract: A head of chip picker is disclosed. The head has a clipping seat and an elastic block. The clipping seat has a body and two arms. The arms are respectively and downwardly extended from two opposite sides of an inner top surface of the body, so a cavity with a wide-top and narrow-bottom shape is constituted among the inner top surface and the arms. The elastic block matches the cavity and is laterally inserted into the cavity. The elastic block is not deformed after inserting into the cavity and provides a flat bottom surface.

公开(公告)号：US11302539B2

公开(公告)日：2022-04-12

申请号：US16987470

申请日：2020-08-07

Applicant: Powertech Technology Inc.

Inventor： Tsung-Han Chiang ,  Chun-Te Lin

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/29 ,  H01L21/683

Abstract: A method for packaging a semiconductor device includes the steps of: disposing a wafer on a first carrier plate; attaching a second carrier plate to a side of the first carrier plate opposite to the wafer; disposing a chip unit on a side of the wafer opposite to the first carrier plate; and covering the wafer and the chip unit with an encapsulation layer. A semiconductor packaging structure is also disclosed.

公开(公告)号：US20220097891A1

公开(公告)日：2022-03-31

申请号：US17217207

申请日：2021-03-30

Applicant: Powertech Technology Inc.

Inventor： Yen Yu CHEN ,  Shin-Kung CHEN ,  Yuan-Jung LU ,  Hsing-Fu PENG

IPC: B65C9/26 ,  B65C9/06

Abstract: A manual labeling device is disclosed. The manual labeling device has a platform, a plurality of positioning elements and a pivoting device. The platform has a labeling area. The positioning elements are mounted on the platform and around the labeling area. The pivoting device is pivotally mounted on one side of the platform and has a pivot shaft and a pivot arm. The operator manually places one product in the labeling area of the platform and the product is fixed in the labeling area by the positioning elements. The operator only pivots the pivot arm and the pivot arm directly aligns with the labeling area. Therefore, it does not take times to align the tool and the labeling area before attaching the label and the label attaching task is simplified to increase the productivity and quality of labeling (units per hour; UPH).

公开(公告)号：US11257747B2

公开(公告)日：2022-02-22

申请号：US16382229

申请日：2019-04-12

Applicant: Powertech Technology Inc.

Inventor： Wen-Jeng Fan ,  Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/66

Abstract: A semiconductor package including a semiconductor chip, a conductive element disposed aside the semiconductor chip, a conductive via disposed on and electrically connected to the conductive element, an insulating encapsulation, and a first circuit structure disposed on the semiconductor chip and the conductive via is provided. A height of the conductive element is less than a height of the semiconductor chip. The insulating encapsulation encapsulates the semiconductor chip, the conductive element, and the conductive via. The conductive via is located between the first circuit structure and the conductive element, and the semiconductor chip is electrically coupled to the conductive via through the first circuit structure.

公开(公告)号：US20210365651A1

公开(公告)日：2021-11-25

申请号：US17037949

申请日：2020-09-30

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Chi-Chung Yu ,  Kai-Hung LIN ,  Tien-Hung LOU

IPC: G06K7/14 ,  G06K19/06

Abstract: An identification method of an integrated circuit chip of the present invention includes identifying a surface structure or an internal structure of an integrated circuit chip, generating a structural information set according to the surface structure or internal structure, converting the structural information set into an identification information set. The identification information set generated by the above-mentioned identification method can be stored in a digital file, and a chip manufacturer requires no visible information printed on an outer surface of the integrated circuit chip such that factory information of the integrated circuit chip can be concealed. When retrieving the malfunctioned or defective integrated circuit chip, the manufacturer can acquire a new generated identification information set by identify the integrated circuit chip and compare the new generated identification information set and the generated identification information set stored in the file to obtain the factory information of the retrieved integrated circuit chip.