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公开(公告)号:US08848391B2
公开(公告)日:2014-09-30
申请号:US13840353
申请日:2013-03-15
Applicant: Invensas Corporation
Inventor: Richard Dewitt Crisp , Belgacem Haba , Wael Zohni
CPC classification number: H05K1/18 , H01L2224/16225 , H05K1/0243 , H05K1/181 , H05K2201/10159 , H05K2201/10454 , Y02P70/611
Abstract: A component is configured for connection with a microelectronic assembly having terminals and a microelectronic element connected with the terminals. The component includes a support structure bearing conductors configured to carry command and address information, and a plurality of contacts coupled to the conductors and configured for connection with the terminals. The contacts have address and command information assignments arranged in a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the contacts at a first sampling rate, and in a second predetermined arrangement for connection with a second type of microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the contacts at a second sampling rate greater than the first sampling rate.
Abstract translation: 元件配置成与具有端子的微电子组件和与端子连接的微电子元件连接。 所述部件包括支承结构,承载配置成承载命令和地址信息的导体,以及耦合到所述导体并被配置为与所述端子连接的多个触点。 触点具有布置在第一预定布置中的地址和命令信息分配,用于与第一类型的微电子组件连接,其中微电子元件被配置为以第一采样率通过触点采集与其耦合的命令和地址信息, 用于与第二类型的微电子组件连接的第二预定布置,其中所述微电子元件被配置为以大于所述第一采样率的第二采样率对所述触点的子集进行所述命令和寻址与其耦合的地址信息进行采样。
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公开(公告)号:US20140273346A1
公开(公告)日:2014-09-18
申请号:US13837724
申请日:2013-03-15
Applicant: INVENSAS CORPORATION
Inventor: Richard Dewitt Crisp , Wael Zohni , Belgacem Haba
IPC: H01L25/00
CPC classification number: H01L25/50 , H01L23/13 , H01L23/3128 , H01L23/49861 , H01L24/50 , H01L25/0655 , H01L25/0657 , H01L27/14683 , H01L2224/04042 , H01L2224/06136 , H01L2224/32145 , H01L2224/32225 , H01L2224/4824 , H01L2224/73215 , H01L2224/92147 , H01L2225/0651 , H01L2225/06562 , H01L2924/15311 , H01L2924/00
Abstract: In a high volume method for manufacturing a microelectronic package, a spacer element and a first die, i.e., microelectronic element, can be attached face-down to a surface of a substrate, contacts on the first die facing a first through opening of the substrate. Then, a second die can be attached face-down atop the first die and the spacer element, contacts on the second die disposed beyond an edge of the first die and facing a second through opening in the substrate. Electrical connections can then be formed between each of the first and second dies and the substrate. The first and second dies can be transferred from positions of a single diced wafer which are selected to maximize compound speed bin yield of the microelectronic package.
Abstract translation: 在用于制造微电子封装的高体积方法中,间隔元件和第一裸片(即微电子元件)可以面朝下地附着到衬底的表面,在第一裸片上的与衬底的第一通孔相接触 。 然后,可以将第二模具面朝下地安装在第一模具和间隔元件的顶部上,在第二模具上接触设置在第一模具的边缘之外并且面向衬底中的第二通孔。 然后可以在第一和第二模具和基板中的每一个之间形成电连接。 第一和第二模具可以从单个切割晶片的位置转移,其被选择为使微电子封装的复合速度仓产量最大化。
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公开(公告)号:US20140268537A1
公开(公告)日:2014-09-18
申请号:US14275098
申请日:2014-05-12
Applicant: INVENSAS CORPORATION
Inventor: Richard Dewitt Crisp , Wael Zohni , Belgacem Haba , Yong Chen
IPC: H05K7/14
CPC classification number: H05K7/1459 , G11C5/063 , H01L23/13 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L25/0655 , H01L2224/4824 , H01L2924/15311
Abstract: In-package fly-by signaling can be provided in a multi-chip microelectronic package having address lines on a package substrate configured to carry address information to a first connection region on the substrate having a first delay from terminals of the package, and the address lines being configured to carry the address information beyond the first connection region to at least to a second connection region having a second delay from the terminals that is greater than the first delay. Address inputs of a first microelectronic element, e.g., semiconductor chip, can be coupled with each of the address lines at the first connection region, and address inputs of a second microelectronic element can be coupled with each of the address lines at the second connection region.
Abstract translation: 可以在具有在封装衬底上的地址线的多芯片微电子封装中提供封装内的飞越信号,该封装衬底被配置为将地址信息传送到具有来自封装端子的第一延迟的衬底上的第一连接区域,并且地址 线路被配置为将地址信息超出第一连接区域至少至少具有来自大于第一延迟的端子的具有第二延迟的第二连接区域。 第一微电子元件(例如,半导体芯片)的地址输入可以与第一连接区域处的每个地址线耦合,并且第二微电子元件的地址输入可以在第二连接区域与每个地址线耦合 。
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公开(公告)号:US08787034B2
公开(公告)日:2014-07-22
申请号:US13839402
申请日:2013-03-15
Applicant: Invensas Corporation
Inventor: Richard Dewitt Crisp , Belgacem Haba , Wael Zohni
CPC classification number: B81B7/007 , H01L23/5384 , H01L25/0652 , H01L2224/12105 , H01L2224/16227 , H01L2224/20 , H01L2224/4824 , H01L2225/1023 , H01L2225/1058 , H01L2225/1076 , H01L2924/15311 , H01L2924/15333
Abstract: A system includes a microelectronic assembly having terminals and a microelectronic element, and a component for connection with the microelectronic assembly. The component includes a support structure bearing conductors configured to carry command and address information, and contacts coupled to the conductors and connected with the terminals of the microelectronic assembly. The contacts have address and command information assignments arranged in a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the contacts at a first sampling rate, and in a second predetermined arrangement for connection with a second type of microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the contacts at a second sampling rate greater than the first sampling rate.
Abstract translation: 一种系统包括具有端子和微电子元件的微电子组件,以及用于与微电子组件连接的部件。 该部件包括支撑结构,承载配置成承载命令和地址信息的导体,以及耦合到导体并与微电子组件的端子连接的触点。 触点具有布置在第一预定布置中的地址和命令信息分配,用于与第一类型的微电子组件连接,其中微电子元件被配置为以第一采样率通过触点采集与其耦合的命令和地址信息, 用于与第二类型的微电子组件连接的第二预定布置,其中所述微电子元件被配置为以大于所述第一采样率的第二采样率对所述触点的子集进行所述命令和寻址与其耦合的地址信息进行采样。
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135.
公开(公告)号:US08670261B2
公开(公告)日:2014-03-11
申请号:US13859271
申请日:2013-04-09
Applicant: Invensas Corporation
Inventor: Richard Dewitt Crisp , Wael Zohni , Belgacem Haba , Frank Lambrecht
IPC: G11C5/06
CPC classification number: G11C5/02 , G11C5/04 , G11C5/06 , G11C5/063 , G11C8/06 , G11C8/10 , G11C8/18 , H01L23/13 , H01L23/3128 , H01L23/36 , H01L23/49816 , H01L23/49827 , H01L24/16 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/92 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/02375 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/06135 , H01L2224/06165 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/45014 , H01L2224/48145 , H01L2224/48227 , H01L2224/4824 , H01L2224/49175 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73265 , H01L2224/9202 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06558 , H01L2225/06562 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/1431 , H01L2924/1434 , H01L2924/1436 , H01L2924/1438 , H01L2924/1443 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/19105 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane.
Abstract translation: 微电子结构具有定义存储阵列的活动元件,以及用于接收指定存储阵列内的位置的地址信息的地址输入。 该结构具有第一表面并且可以具有在第一表面处露出的端子。 终端可以包括第一终端,并且该结构可以被配置为将在第一终端接收的地址信息传送到地址输入。 每个第一终端可以具有包括一个或多个地址输入的信号分配。 第一端子设置在与第一表面垂直的理论平面的第一和第二相对侧上,其中设置在第一侧上的第一端子的信号分配是设置在第二端上的第一端子的信号分配的镜像 理论面的一面。
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136.
公开(公告)号:US20130286707A1
公开(公告)日:2013-10-31
申请号:US13859271
申请日:2013-04-09
Applicant: Invensas Corporation
Inventor: Richard Dewitt Crisp , Wael Zohni , Belgacem Haba , Frank Lambrecht
IPC: G11C5/06
CPC classification number: G11C5/02 , G11C5/04 , G11C5/06 , G11C5/063 , G11C8/06 , G11C8/10 , G11C8/18 , H01L23/13 , H01L23/3128 , H01L23/36 , H01L23/49816 , H01L23/49827 , H01L24/16 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/92 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/02375 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/06135 , H01L2224/06165 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/45014 , H01L2224/48145 , H01L2224/48227 , H01L2224/4824 , H01L2224/49175 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73265 , H01L2224/9202 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06558 , H01L2225/06562 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/1431 , H01L2924/1434 , H01L2924/1436 , H01L2924/1438 , H01L2924/1443 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/19105 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane.
Abstract translation: 微电子结构具有定义存储阵列的活动元件,以及用于接收指定存储阵列内的位置的地址信息的地址输入。 该结构具有第一表面并且可以具有在第一表面处露出的端子。 终端可以包括第一终端,并且该结构可以被配置为将在第一终端接收的地址信息传送到地址输入。 每个第一终端可以具有包括一个或多个地址输入的信号分配。 第一端子设置在与第一表面垂直的理论平面的第一和第二相对侧上,其中设置在第一侧上的第一端子的信号分配是设置在第二端上的第一端子的信号分配的镜像 理论面的一面。
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