公开(公告)号：US20240221133A1

公开(公告)日：2024-07-04

申请号：US18148244

申请日：2022-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Niraj Nandan ,  Rajasekhar Allu ,  Mihir Narenda Mody ,  Ankur Ankur ,  Pandy Kalimuthu

IPC: G06T5/00 ,  G06T1/60

CPC classification number: G06T5/006 ,  G06T1/60

Abstract: Various embodiments disclosed herein relate to distorted pixel correction, and more specifically to producing an output image using variable-sized groupings of lines of pixels of an input image. An example embodiment includes a method of using variable-sized pixel groupings when processing distorted image data. The method comprises identifying a context of an image captured by an imaging system, wherein the image comprises lines of pixels that form a distorted representation of a scene, identifying, based on the context of the image, a mapping of variable-sized groupings of the lines to memory ranges in a buffer, wherein an image processing subsystem produces block rows of an output image based on the mapping, and wherein a size of each of the variable-sized groupings varies based on how many of the lines the image processing subsystem uses to produce each of the block rows, and supplying the mapping to the image processing subsystem.

公开(公告)号：US12010330B2

公开(公告)日：2024-06-11

申请号：US18123432

申请日：2023-03-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hideo Tamama

IPC: H04N19/176 ,  H04N19/117 ,  H04N19/14 ,  H04N19/82 ,  H04N19/86 ,  H04N19/186

CPC classification number: H04N19/176 ,  H04N19/117 ,  H04N19/14 ,  H04N19/82 ,  H04N19/86 ,  H04N19/186

Abstract: A method of de-blocking filtering a processed video is provided. The processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. A current block of the plurality of blocks includes vertical edges and horizontal edges. The processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. A boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. The set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. The vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block.

公开(公告)号：US20240104922A1

公开(公告)日：2024-03-28

申请号：US18521356

申请日：2023-11-28

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hetul Sanghvi ,  Manoj Koul

IPC: G06V10/98 ,  G06F11/07 ,  G06T5/00 ,  G06V10/36

CPC classification number: G06V10/98 ,  G06F11/0736 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06T5/00 ,  G06V10/36 ,  G06T7/0002

Abstract: Systems and articles of manufacture provide an efficient safety mechanism for signal processing hardware. An example system includes a hardware accelerators, including a first hardware accelerator, and a second hardware accelerator coupled to the first hardware accelerator. Each of the first and second hardware accelerators includes a protected memory and an unprotected memory, and at least one of the hardware accelerators has an outlier filter. The system also includes a memory coupled to the hardware accelerators; and interface protectors, including a first interface protector coupled between the first hardware accelerator and the memory; a second interface protector coupled between the first hardware accelerator, the memory, and the second hardware accelerator; and a third interface protector coupled between the second hardware accelerator and the memory.

公开(公告)号：US20230353789A1

公开(公告)日：2023-11-02

申请号：US18219788

申请日：2023-07-10

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Mullangi Venkata Ratna Reddy

IPC: H04N19/80 ,  H04N19/86 ,  H04N19/423

CPC classification number: H04N19/80 ,  H04N19/423 ,  H04N19/86

Abstract: A de-blocking filter includes a reconstructed memory that is configured to store reconstructed pixels corresponding to a current macroblock of a video image to be filtered. The current macroblock includes a set of sub-blocks, each sub-block having horizontal edges and vertical edges. An internal pixel buffer in the de-blocking filter is configured to store pixels corresponding to the set of sub-blocks from the reconstructed memory, and to store partially filtered pixels corresponding to a set of partially filtered macroblocks. An edge order controller in the de-blocking filter is configured to load the pixels corresponding to the set of sub-blocks into a filter engine from the internal pixel buffer, to filter the set of sub-blocks, such that, at least one horizontal edge is filtered before filtering all vertical edges of the set of sub-blocks.

公开(公告)号：US11798128B2

公开(公告)日：2023-10-24

申请号：US16745589

申请日：2020-01-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Brian Okchon Chae ,  Niraj Nandan ,  Anthony Joseph Lell ,  Mihir Mody

IPC: G06T3/40 ,  G06V10/32 ,  G06V10/96 ,  G06V10/98 ,  H04N1/00

CPC classification number: G06T3/4023 ,  G06V10/32 ,  G06V10/96 ,  G06V10/993 ,  H04N1/00005 ,  H04N1/00021 ,  H04N1/00034 ,  H04N1/00082 ,  G06T2207/10016

Abstract: An image data frame is received from an external source. An error concealment operation is performed on the received image data frame in response to determining that a first frame size of the received image data frame is erroneous. The first frame size of the image data frame is determined to be erroneous based on at least one frame synchronization signal associated with the image data frame. An image processing operation is performed on the received image data frame on which the error concealment operation has been performed, thereby enabling an image processing module to perform the image processing operation without entering into a deadlock state and thereby prevent a host processor from having to execute hardware resets of deadlocked modules.

公开(公告)号：US11715188B1

公开(公告)日：2023-08-01

申请号：US17682735

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Veeramanikandan Raju ,  Niraj Nandan ,  Samuel Paul Visalli ,  Jason A. T. Jones ,  Kedar Satish Chitnis ,  Gregory Raymond Shurtz ,  Prithvi Shankar Yeyyadi Anantha ,  Sriramakrishnan Govindarajan

IPC: G05B23/02 ,  G06T1/20 ,  G06T7/00 ,  G06T3/40 ,  H04N17/00

CPC classification number: G06T7/0002 ,  G05B23/0259 ,  G06T1/20 ,  G06T3/40 ,  G06T7/97 ,  G06T2207/10016 ,  H04N17/00

Abstract: An electronic device may be configured to detect a fault in imaging and vision hardware accelerators. The electronic device may include a controller configured to select a first golden input frame of multiple golden input frames to perform a first self-test, and retrieve a first reference image signature corresponding to the first golden input frame. The electronic device may include a hardware accelerator module configured to obtain the first golden input frame, and generate a first output frame based on the first golden input frame. The electronic device may include a signature generator configured to generate a first generated image signature based on the first output frame. The electronic device may include a signature comparison module configured to compare the first generated image signature to the first reference image signature in order to determine whether the hardware accelerator module includes a fault at a first time.

公开(公告)号：US11599975B2

公开(公告)日：2023-03-07

申请号：US16930342

申请日：2020-07-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajasekhar Reddy Allu ,  Niraj Nandan ,  Mihir Narendra Mody ,  Gang Hua ,  Brian Okchon Chae ,  Shashank Dabral ,  Hetul Sanghvi ,  Vikram VijayanBabu Appia ,  Sujith Shivalingappa

IPC: G06T5/00 ,  G06T3/00 ,  G06T3/40 ,  G06T5/20 ,  G06T5/40 ,  G06T7/11 ,  G06T1/60

Abstract: An apparatus and method for geometrically correcting a distorted input frame and generating an undistorted output frame. The apparatus includes an external memory block that stores the input frame, a counter block to compute output coordinates of the output frame for a region based on a block size of the region, a back mapping block to generate input coordinates corresponding to each of the output coordinates, a bounding module to compute input blocks corresponding to each of the input coordinates, a buffer module to fetch data corresponding to each of the input blocks, an interpolation module to interpolate data from the buffer module and a display module that receives the interpolated data for each of the regions and stitch an output image. The method includes determining the size of the output block based on a magnification data.

公开(公告)号：US11546562B2

公开(公告)日：2023-01-03

申请号：US17497560

申请日：2021-10-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Shashank Dabral ,  Rajasekhar Allu ,  Niraj Nandan

IPC: H04N1/60 ,  H04N9/04 ,  G06T1/20 ,  H04N9/67

Abstract: An image signal processor includes a first matrix processing circuit, a post processing circuit, a second matrix processing circuit, and a split visual and analytics circuit. The first matrix processing circuit is configured to receive a plurality of component images generated based on an image captured by an image sensor and generate a plurality of first matrix outputs based on the plurality of component images. The post processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a first luminance component of the image and a chrominance component of the image. The second matrix processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a second luminance component of the image and a saturation component of the image. The split visual and analytics circuit is configured to generate visual and analytic data of the image.

公开(公告)号：US11341606B2

公开(公告)日：2022-05-24

申请号：US16930543

申请日：2020-07-16

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Brian Chae ,  Shashank Dabral ,  Niraj Nandan ,  Hetul Sanghvi

IPC: G06K9/32 ,  G06T3/40 ,  G06T1/20 ,  H04N1/393

Abstract: An apparatus for scaling images is provided that includes at least two input ports, a scaling component coupled to the at least two input ports, the scaling component including a plurality of scalers, the scaling component configurable to map any scaler to any input port of the at least two input ports and configurable to map more than one scaler to any input port, and a memory coupled to the at least two input ports and to outputs of the plurality of scalers, the memory configured to store image data for each input port and scaled image data output by the plurality of scalers.

公开(公告)号：US20220070499A1

公开(公告)日：2022-03-03

申请号：US17523541

申请日：2021-11-10

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Mullangi Venkata Ratna Reddy

IPC: H04N19/80 ,  H04N19/423 ,  H04N19/86

Abstract: A de-blocking filter includes a reconstructed memory that is configured to store reconstructed pixels corresponding to a current macroblock of a video image to be filtered. The current macroblock includes a set of sub-blocks, each sub-block having horizontal edges and vertical edges. An internal pixel buffer in the de-blocking filter is configured to store pixels corresponding to the set of sub-blocks from the reconstructed memory, and to store partially filtered pixels corresponding to a set of partially filtered macroblocks. An edge order controller in the de-blocking filter is configured to load the pixels corresponding to the set of sub-blocks into a filter engine from the internal pixel buffer, to filter the set of sub-blocks, such that, at least one horizontal edge is filtered before filtering all vertical edges of the set of sub-blocks.