公开(公告)号：US10074656B1

公开(公告)日：2018-09-11

申请号：US15479294

申请日：2017-04-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Li-Wei Feng ,  Chien-Ting Ho ,  Wen-Chieh Lu ,  Li-Wei Liu

IPC: H01L27/108

Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.

公开(公告)号：US20180247943A1

公开(公告)日：2018-08-30

申请号：US15889182

申请日：2018-02-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Shih-Fang Tzou ,  Chien-Ting Ho ,  Ying-Chiao Wang ,  Yu-Ching Chen ,  Hui-Ling Chuang ,  Kuei-Hsuan Yu

IPC: H01L27/108

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L27/10823

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

公开(公告)号：US20180226408A1

公开(公告)日：2018-08-09

申请号：US15452746

申请日：2017-03-08

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ying-Chiao Wang ,  Tsung-Ying Tsai ,  Kai-Ping Chen ,  Chien-Ting Ho

IPC: H01L27/108 ,  H01L23/528

CPC classification number: H01L27/10885 ,  H01L23/5283 ,  H01L27/10897

Abstract: A semiconductor device includes a substrate, plural active areas, plural bit lines and plural dummy bit lines. The substrate includes a cell region and a periphery region, and the active areas are defined on the substrate. The bit lines are disposed on the substrate, within the cell region and across the active areas. The dummy bit lines are disposed at a side of the bit lines, wherein the dummy bit lines are in contact with each other and have different pitches therebetween.

公开(公告)号：US20180226251A1

公开(公告)日：2018-08-09

申请号：US15885827

申请日：2018-02-01

Applicant: UNITED MICROELECTRONICS CORP. ,  FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.

Inventor： Kai-Ping Chen ,  Kuei-Hsuan Yu ,  Chiu-Hsien Yeh ,  Li-Wei Feng

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/0338 ,  H01L21/02118 ,  H01L21/02356 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852

Abstract: A method for forming patterns of semiconductor device is provided in the present invention, with steps of filling up first self-assembly material in first openings in a dielectric layer, phase-separating the first self-assembly material to form a first portion and a second portion surrounding the first portion, removing the first portion and performing a first etch process to form a first mask pattern in a mask layer, forming a second dielectric layer and repeating the above steps to form a second mask pattern in the mask layer, wherein the second mask pattern is aligned with the first mask pattern to form a common mask pattern.

公开(公告)号：US20180197981A1

公开(公告)日：2018-07-12

申请号：US15916261

申请日：2018-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Jyh-Shyang Jenq

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/66803

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first fin-shaped structure thereon; forming a spacer adjacent to the first fin-shaped structure; using the spacer as mask to remove part of the substrate for forming a second fin-shaped structure, wherein the second fin-shaped structure comprises a top portion and a bottom portion; and forming a doped portion in the bottom portion of the second fin-shaped structure.

公开(公告)号：US20170278947A1

公开(公告)日：2017-09-28

申请号：US15196024

申请日：2016-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chih-Kai Hsu ,  Jyh-Shyang Jenq

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L29/66545 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: A method of forming a semiconductor fin structure is provided. A substrate is provided, which has at least two sub regions and a dummy region disposed therebetween. A recess is disposed in each sub region. A semiconductor layer is formed to fill the recesses. A patterned mask layer is formed on the semiconductor layer in the sub regions and on the substrate in the dummy region. The substrate and the semiconductor layer are removed by using the patterned mask layer as a mask, thereby forming a plurality of fin structures in the sub regions and a plurality of dummy fin structures in the dummy region. The present invention further provides a semiconductor fin structure.

公开(公告)号：US09773790B1

公开(公告)日：2017-09-26

申请号：US15456605

申请日：2017-03-13

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chien-Ting Ho ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Yu-Chieh Lin

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/45

CPC classification number: H01L27/10823 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10897

Abstract: A semiconductor device includes a substrate including at least a memory region defined therein and a plurality of memory cells formed in the memory region, a plurality of first connecting structures, a plurality of second connecting structures, a plurality of dummy nodes respectively disposed on the first connecting structures, and a plurality of first storage nodes respectively disposed on the second connecting structures. The first connecting structures respectively include a conductive portion and a first metal portion, and the second connecting structures respectively include the conductive portion and a second metal portion. The first metal portion and the second metal portion include the same material. And the first metal portion and the second metal portion include different heights.

公开(公告)号：US20170263732A1

公开(公告)日：2017-09-14

申请号：US15481419

申请日：2017-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Yi-Fan Li ,  Kun-Hsin Chen ,  Tong-Jyun Huang ,  Jyh-Shyang Jenq ,  Nan-Yuan Huang

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26546 ,  H01L29/1054 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor device preferably includes a substrate, a fin-shaped structure on the substrate, a buffer layer on the fin-shaped structure, and an epitaxial layer on the buffer layer. Preferably, the buffer layer is made of silicon germanium and including three or more than three elements. The buffer layer also includes dopants selected from the group consisting of P, As, Sb, Bi, C, and F.

公开(公告)号：US20170178972A1

公开(公告)日：2017-06-22

申请号：US15447126

申请日：2017-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yu Chang ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Chien-Ting Lin ,  Yi-Ren Chen ,  Shou-Wei Hsieh ,  Hsin-Yu Chen ,  Chun-Hao Lin

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/02129 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66803

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process.

公开(公告)号：US20170133479A1

公开(公告)日：2017-05-11

申请号：US14957623

申请日：2015-12-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ying-Chiao Wang ,  Chao-Hung Lin ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Li-Wei Feng ,  Yu-Hsiang Hung

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/033 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/32

CPC classification number: H01L29/6656 ,  H01L21/0332 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/32 ,  H01L29/66545 ,  H01L29/78

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon, a first spacer around the gate structure, and a contact etch stop layer (CESL) adjacent to the first spacer; forming a cap layer on the gate structure, the first spacer, and the CESL; and removing part of the cap layer for forming a second spacer adjacent to the CESL.