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    Woven mesh interconnect
    131.
    发明授权
    Woven mesh interconnect 失效
    编织网状互连

    公开(公告)号：US06222126B1

    公开(公告)日：2001-04-24

    申请号：US09145089

    申请日：1998-09-01

    Applicant: Andrew H. Strange ,  Arthur Millay ,  Leonard S. Buchoff ,  Steven K. Mac Innes ,  Daniel W. Rassier

    Inventor： Andrew H. Strange ,  Arthur Millay ,  Leonard S. Buchoff ,  Steven K. Mac Innes ,  Daniel W. Rassier

    IPC: H02G300

    CPC classification number: H01R13/2492 ,  H05K1/038 ,  H05K2201/0281 ,  H05K2201/029 ,  Y10T442/107 ,  Y10T442/109 ,  Y10T442/131

    Abstract: An electrical interconnect includes a woven mesh in which an array of parallel wires is retained in spaced relation by a transverse array of nonconducting strands, the mesh being enclosed or encased within a resilient matrix. The conductive wires are on a close pitch to yield greater current carrying capacity and achieve a lower more stable resistance. With this construction a great number of wires are in contact with each contact pad to yield greater current carrying capacity and corresponding lower resistance. The closer pitch wires also provide greater redundancy of contact points. This structure can be custom configured in as many layers or in a variety of shapes as is desirable to achieve a given electrical performance. The woven mesh can be wrapped around a shaped substrate to provide electrical connections in a desired shape. The woven mesh interconnect can be integrated as part of a boot, wherein the boot receives an electrical device therein and the woven mesh interconnect provides electrical connection from the device within the boot to outside the boot. The woven mesh interconnect can be layered and shaped to form an interconnect which not only provides electrical interconnection but also provides a biasing force due to the shape of the device.

    Abstract translation: 电互连包括编织网，其中平行线的阵列由非导体股的横向阵列以间隔的关系保持，网被包围或包裹在弹性矩阵内。 导线处于紧密的间距处，以产生更大的载流能力并实现更低的更稳定的电阻。 利用这种结构，大量的电线与每个接触垫接触以产生更大的载流能力和相应的较低电阻。 更靠近的节距线还提供更大的接触点冗余度。 这种结构可以按照实现给定的电气性能所需的多层或多种形状来定制配置。 编织网可以缠绕成形的基底以提供所需形状的电连接。 机织网状互连可以被集成为靴子的一部分，其中靴子在其中容纳电气装置，并且编织网状互连提供从靴子内的装置到靴子外部的电连接。 机织网状互连可以被层叠和成形以形成互连，其不仅提供电互连，而且还由于器件的形状而提供偏置力。

    Method for reducing coefficient of thermal expansion in chip attach packages
    132.
    发明授权
    Method for reducing coefficient of thermal expansion in chip attach packages 失效
    降低芯片连接封装热膨胀系数的方法

    公开(公告)号：US6136733A

    公开(公告)日：2000-10-24

    申请号：US874902

    申请日：1997-06-13

    Applicant: Lawrence Robert Blumberg ,  Robert Maynard Japp ,  William John Rudik ,  John Frank Surowka

    Inventor： Lawrence Robert Blumberg ,  Robert Maynard Japp ,  William John Rudik ,  John Frank Surowka

    IPC: B32B5/28 ,  H05K1/03 ,  B32B5/26 ,  C09J5/02

    CPC classification number: B32B5/28 ,  H05K1/036 ,  H05K1/0366 ,  H05K2201/029 ,  H05K2201/0293 ,  H05K2201/068 ,  Y10T29/4913

    Abstract: A simple, inexpensive, drillable, reduced CTE laminate and circuitized structures comprising the reduced CTE laminate, is provided. The reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0.05% to 0.3%, preferably from about 0.08% to 0.10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The present invention also generally relates to a method for reducing the CTE of circuitized structures, and to methods for making reduced CTE laminate and circuitized structures comprising reduced CTE laminate. The method for making reduced CTE laminate and laminate structures comprises the following steps: providing non-woven quartz mat; providing a prepreg, preferably B-stage cured to not more than about 40%, preferably not more than 30% of full cure; sandwiching the non-woven quartz mat between two layers of prepreg, and reflowing the resin of the prepreg into the quartz mat. Optionally, the reduced CTE laminate is sandwiched between two layers of metal, preferably copper.

    Abstract translation: 提供了一种简单，便宜，可钻，减少的CTE层压板和包括减小的CTE层压板的电路结构。 减少的CTE层压材料包括：约40％至75％，优选约55％至65％的树脂; 约0.05％至0.3％，优选约0.08％至0.10％的固化剂; 约25％至60％，优选约30％至40％的织布; 约1％至15％，优选约5％至10％体积的无纺石英垫。 本发明还通常涉及一种用于减小电路化结构的CTE的方法，以及用于制造减少的CTE层压体和包括减少的CTE层压体的电路化结构的方法。 制造减薄的CTE层压板和层压结构的方法包括以下步骤：提供无纺石英垫; 提供预浸料，优选B阶固化至不超过完全固化的约40％，优选不超过30％; 将无纺石英垫夹在两层预浸料之间，并将预浸料坯的树脂回流到石英垫中。 任选地，还原的CTE层压体夹在两层金属之间，优选为铜。

    Multi-layer semiconductor package substrate with thermally-conductive prepeg layer
    136.
    发明授权
    Multi-layer semiconductor package substrate with thermally-conductive prepeg layer 失效
    具有导热性预浸层的多层半导体封装基板

    公开(公告)号：US5500555A

    公开(公告)日：1996-03-19

    申请号：US225860

    申请日：1994-04-11

    Applicant: Tom Ley

    Inventor： Tom Ley

    IPC: H01L23/367 ,  H01L23/373 ,  H05K1/02 ,  H05K3/46 ,  H01L23/053 ,  H01L23/12 ,  H01L23/14

    CPC classification number: H05K3/4641 ,  H01L23/367 ,  H01L23/3735 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49109 ,  H05K1/0203 ,  H05K1/0207 ,  H05K2201/0281 ,  H05K2201/029 ,  H05K2201/09681

    Abstract: Improved thermal characteristics are obtained in a multi-layer substrate for mounting a semiconductor device. A prepeg layer disposed in close proximity to or immediately adjacent to a semiconductor device is formed incorporating an integral, thermally-conductive mesh or screen. The prepeg layer is preferably a sandwich structure of two BT-resin layers (films), between which is disposed a copper screen. In this manner, heat is conducted away from an operating device by an integral part of the substrate, without the need for additional slugs or heat sink structures. Utility for multichip modules is also disclosed.

    Abstract translation: 在用于安装半导体器件的多层基板中获得改进的热特性。 设置在靠近或紧邻半导体器件的预成型层被形成为包括一体的导热网或筛网。 预成型层优选为两个BT-树脂层（膜）的夹层结构，其间设置有铜屏。 以这种方式，通过衬底的整体部分将热量从操作装置传导出来，而不需要额外的s块或散热器结构。 还公开了用于多芯片模块的实用程序。

    Process for the production of copper-clad laminate
    138.
    发明授权
    Process for the production of copper-clad laminate 失效
    生产覆铜层压板的工艺

    公开(公告)号：US5435877A

    公开(公告)日：1995-07-25

    申请号：US56536

    申请日：1993-05-05

    Applicant: Kenji Ishii ,  Yoshinori Kondo ,  Hiroyuki Matsumoto ,  Takamasa Nakai

    Inventor： Kenji Ishii ,  Yoshinori Kondo ,  Hiroyuki Matsumoto ,  Takamasa Nakai

    IPC: B29C70/08 ,  B32B15/08 ,  B32B37/18 ,  H05K1/03 ,  H05K1/09 ,  B32B31/12 ,  B32B31/18 ,  B32B31/20 ,  B32B31/22

    CPC classification number: B32B37/182 ,  B29C70/088 ,  B32B15/08 ,  B32B37/04 ,  B32B37/06 ,  H05K1/0366 ,  H05K1/09 ,  B32B2305/08 ,  B32B2311/12 ,  H05K2201/029 ,  H05K2201/0355 ,  Y10T156/1075

    Abstract: A process for the production of a copper-clad laminate which is improved in dimensional accuracy and freedom from bow and twist and shows nearly the same values of dimensional accuracy, thermal expansion coefficient and elastic modulus in the length and width directions, the process using:a prepreg (I) comprising a glass cloth (I-1) having a thickness of 190.+-.20 .mu.m, a weight of 210.+-.20 g/m.sup.2, warp and weft counts of 35 to 38 yarns/25 mm and a warp and weft difference of 2 yarns or less in count, anda copper foil (II) having a ductility, measured in atmosphere at 180.degree. C. in length and width directions, of at least 10% when it is a 1/2 oz/Ft.sup.2 foil, at least 15% when it is a 1 oz/Ft.sup.2 foil and at least 20% when it is a 2 oz/Ft.sup.2 foil, andthe set of the prepreg or prepregs and copper foil or copper foils is laminate-molded by curing it under predetermined heat in a laminate-molding step using a press machine, removing the application of pressure and then cooling the resultant laminate in the press machine.

    Abstract translation: 一种生产覆铜层压板的方法，其尺寸精度提高并且不受弯曲和弯曲，并且在长度和宽度方向上显示出几乎相同的尺寸精度，热膨胀系数和弹性模量的值，该方法使用： 包括厚度为190 +/-20μm，重量为210 +/- 20g / m 2的玻璃布（I-1），经纬度为35至38根/ 25mm的预浸料（I） 以及计数为2根以下的纬纱和纬纱的差异，以及在长度和宽度方向的180℃下在大气中测定的具有延展性的铜箔（II）为1 / 2盎司/ Ft2箔，当为1盎司/ Ft2箔时为至少15％，当为2盎司/ Ft2箔时为至少20％，并且预浸料坯或预浸料和铜箔或铜箔的组合为层压体 通过使用压制机在层压成型步骤中在预定热下固化来模塑，除去施加压力，然后冷却所得到的层 在压机中。

    High-frequency multilayer printed circuit board
    140.
    发明授权
    High-frequency multilayer printed circuit board 失效
    高频多层印刷电路板

    公开(公告)号：US4812792A

    公开(公告)日：1989-03-14

    申请号：US44689

    申请日：1987-05-01

    Applicant: Joseph D. Leibowitz

    Inventor： Joseph D. Leibowitz

    IPC: B32B15/08 ,  H05K1/03 ,  H05K1/05 ,  H05K3/42 ,  H05K3/46 ,  H01P3/08 ,  H05K3/06

    CPC classification number: B32B15/08 ,  H05K1/0207 ,  H05K3/4641 ,  H05K1/0243 ,  H05K1/034 ,  H05K2201/015 ,  H05K2201/0287 ,  H05K2201/029 ,  H05K2201/0323 ,  H05K2201/068 ,  H05K3/429

    Abstract: A circuit board having multiple layers of a dielectric material, multiple layers of a conductive metal and multiple layers of graphite bonded together to form a composite multilayer printed circuit board having a desired coefficient of expansion and having strip and microstrip transmission lines for electrically connecting very high frequency electronic components mounted on the circuit board. The multiple layers of graphite are positioned in a symmetrical manner with respect to the thickness of the circuit board and selected in number to provide the circuit board with a desired coefficient of expansion. In addition, at least some of the layers of graphite are positioned in close proximity to some of the layers of conductive metal to provide enhanced thermal conduction from the mounted components.

    Abstract translation: 具有多层介电材料的电路板，多层导电金属和多层石墨结合在一起以形成具有所需膨胀系数的复合多层印刷电路板，并具有用于电连接非常高的带状和微带传输线 频率电子元件安装在电路板上。 多层石墨相对于电路板的厚度以对称的方式定位，并且在数量上选择以为电路板提供所需的膨胀系数。 此外，至少一些石墨层被定位成紧邻导电金属的一些层，以提供来自所安装部件的增强的热传导。

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