公开(公告)号：US20240292535A1

公开(公告)日：2024-08-29

申请号：US18651724

申请日：2024-05-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kosuke NISHIO

IPC: H05K1/11 ,  H05K1/03

CPC classification number: H05K1/115 ,  H05K1/0393 ,  H05K2201/0141 ,  H05K2201/015 ,  H05K2201/096

Abstract: A multilayer board in which interlayer connection conductors include one or more first interlayer connection conductors in a first region and passing through any of a first insulator layer, a second insulator layer, and a third insulator layer in an up-down direction and a second interlayer connection conductor located in a second region and passing through the third insulator layer in the up-down direction. The second interlayer connection conductor is joined to a conductor and a second conductor layer. An area of the second interlayer connection conductor viewed in the up-down direction is larger than a minimum value of areas of the one or more first interlayer connection conductors viewed in the up-down direction.

公开(公告)号：US20240276632A1

公开(公告)日：2024-08-15

申请号：US18625063

申请日：2024-04-02

Applicant: CelLink Corporation

Inventor： Kevin Michael Coakley ,  Malcolm Parker Brown ,  Dongao Yang ,  Michael Lawrence Miller ,  Paul Henry Lego

IPC: H05K1/02 ,  H01M50/519 ,  H05K1/11 ,  H05K3/00 ,  H05K3/04 ,  H05K3/06 ,  H05K3/20 ,  H05K3/28 ,  H05K3/44 ,  H05K3/46

CPC classification number: H05K1/0201 ,  H01M50/519 ,  H05K1/118 ,  H05K3/007 ,  H05K3/0073 ,  H05K3/06 ,  H05K3/20 ,  H05K3/281 ,  H05K3/4623 ,  H05K3/046 ,  H05K3/064 ,  H05K3/44 ,  H05K3/445 ,  H05K2201/0145 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/10037 ,  H05K2203/066 ,  Y02E60/10 ,  Y10T29/49156

Abstract: A method of forming a flexible interconnect circuit is described. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators.

公开(公告)号：USRE49929E1

公开(公告)日：2024-04-16

申请号：US17528405

申请日：2021-11-17

Applicant: Sumitomo Electric Industries, Ltd. ,  SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.

Inventor： Shingo Kaimori ,  Masaaki Yamauchi ,  Kentaro Okamoto ,  Satoshi Kiya ,  Kazuo Murata

IPC: H05K1/03 ,  B32B15/08 ,  B32B15/082 ,  B32B15/20 ,  B32B27/20 ,  B32B27/30 ,  H05K1/02 ,  H05K1/09 ,  H05K3/00 ,  H05K3/38

CPC classification number: H05K1/0373 ,  B32B15/08 ,  B32B15/082 ,  B32B15/20 ,  B32B27/20 ,  B32B27/30 ,  H05K1/0271 ,  H05K1/03 ,  H05K1/034 ,  H05K1/09 ,  H05K3/0055 ,  H05K3/381 ,  H05K2201/015 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/029 ,  H05K2201/0355 ,  H05K2201/068 ,  H05K2203/1194

Abstract: A first embodiment of a substrate for a high-frequency printed wiring board according to the present disclosure is directed to a substrate for a high-frequency printed wiring board, the substrate including: a dielectric layer including a fluororesin and an inorganic filler; and a copper foil layered on at least one surface of the dielectric layer, wherein a surface of the copper foil at the dielectric layer side has a maximum height roughness (Rz) of less than or equal to 2 μm, and a ratio of the number of inorganic atoms of the inorganic filler to the number of fluorine atoms of the fluororesin in a superficial region of the dielectric layer at the copper foil side is less than or equal to 0.08.

公开(公告)号：US20240043614A1

公开(公告)日：2024-02-08

申请号：US18039847

申请日：2021-12-03

Applicant: CHEMOURS-MITSUI FLUOROPRODUCTS CO., LTD

Inventor： GEN EGASHIRA ,  MASAKI MUGISAWA ,  KAZUYA ICHINOSE ,  KEIGO HIGASHIDA

IPC: C08G65/40 ,  C08J5/24 ,  H05K1/03

CPC classification number: C08G65/4006 ,  C08J5/24 ,  H05K1/0366 ,  C08J2365/00 ,  C08G2650/48 ,  H05K2201/015

Abstract: Provided is a novel fluororesin useful as an electronic substrate material for high speed transmission. The fluorine resin has the structure of Formula (I), wherein n is within a range of 1 to 100, L has the structure in Formula (II) or Formula (III), R1 and R2 are independently hydrogen atoms, C1 to C10 alkyl groups, C1 to C10 haloalkyl groups, or C6 to C10 aryl groups, or R1 and R2 may be combined to form a ring structure that may include a substituent, R3 and R4 are each independently hydrogen, fluorine, C1 to C10 saturated or unsaturated hydrocarbon groups in which a portion of or all hydrogens may be substituted with a halogen, and C6 to C10 aryl groups in which a portion of or all hydrogens may be substituted with a halogen, and X is a group containing an olefinic carbon-carbon double bond or a carbon-carbon triple bond and at least one fluorine atom.

公开(公告)号：US11818838B2

公开(公告)日：2023-11-14

申请号：US16662618

申请日：2019-10-24

Applicant: TAIWAN UNION TECHNOLOGY CORPORATION

Inventor： Wen-Ren Chen ,  Shi-Ing Huang ,  Shur-Fen Liu

IPC: H05K1/03 ,  H05K3/02

CPC classification number: H05K1/036 ,  H05K3/022 ,  H05K2201/015 ,  H05K2201/0195 ,  H05K2201/029 ,  H05K2201/0293

Abstract: A metal-clad laminate is provided. The metal-clad laminate includes:



a dielectric layer, which has a first reinforcing material and a dielectric material formed on the surface of the first reinforcing material, wherein the dielectric material includes 60 wt % to 80 wt % of a first fluoropolymer and 20 wt % to 40 wt % of a first filler;
an adhesive layer, which is disposed on at least one side of the dielectric layer and includes an adhesive material, wherein the adhesive material has 60 wt % to 70 wt % of a second fluoropolymer and 30 wt % to 40 wt % of a second filler; and
a metal foil, which is disposed on the other side of the adhesive layer that is opposite to the dielectric layer,
wherein the melting point of the second fluoropolymer is lower than the melting point of the first fluoropolymer.

公开(公告)号：US20230363090A1

公开(公告)日：2023-11-09

申请号：US18353471

申请日：2023-07-17

Applicant: DAIKIN INDUSTRIES, LTD.

Inventor： Hirokazu KOMORI ,  Tatsuya Higuchi ,  Kenzo Takahashi ,  Masahiko Kawamura ,  Koji Yokotani ,  Junpei Terada ,  Nobuyuki Komatsu

IPC: H05K1/03 ,  C08J5/18 ,  C08J5/12

CPC classification number: H05K1/0326 ,  C08J5/18 ,  C08J5/121 ,  C08J2327/18 ,  C08J2327/24 ,  H05K2201/0355 ,  H05K2201/015

Abstract: A fluororesin film including a fluorine-containing composition, wherein the oxygen element percentage as measured when heat treatment is performed at 180° C. for 3 minutes and then the state of one or both surfaces of the film is observed by scanning X-ray photoelectron spectroscopy (XPS/ESCA) is 1.35 atom % or more, and an absolute value of the rate of dimensional change in MD and TD before and after heat treatment as measured when the film is heat-treated at 180° C. for 10 minutes and then cooled to room temperature is 2% or less. Also disclosed is a copper-clad laminate, including copper foil and the fluororesin film; a substrate for circuit, including the copper-clad laminate; and a method for producing the copper-clad laminate.

公开(公告)号：US11785713B2

公开(公告)日：2023-10-10

申请号：US17425713

申请日：2020-01-13

Applicant: AMOGREENTECH CO., LTD.

Inventor： Jeong-Sang Yu ,  Young-Suk Oh ,  Taek-Min Kim

IPC: H05K1/02 ,  H05K3/06 ,  H05K3/46 ,  H05K1/18

CPC classification number: H05K1/028 ,  H05K1/0201 ,  H05K3/06 ,  H05K3/4644 ,  H05K1/181 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/10189

Abstract: A flexible cable jumper structure and manufacturing method thereof. The flexible cable jumper device of the present disclosure includes a cover layer, a first metal layer stacked on the cover layer and having a circuit pattern formed thereon, a first dielectric layer stacked on the first metal layer, a first adhesive layer applied on the first dielectric layer, a second metal layer stacked on the first dielectric layer to which the first adhesive layer is applied and having a circuit pattern formed thereon, a heat-resistant layer stacked on the second metal layer, and a terminal layer formed in one region of the heat-resistant layer and electrically connected to the first metal layer and the second metal layer.

公开(公告)号：US11777186B2

公开(公告)日：2023-10-03

申请号：US16647319

申请日：2018-09-14

Applicant: ALLEN-VANGUARD CORPORATION

Inventor： Sulav Adhikari ,  Ernst Wallisch, Jr.

IPC: H01P1/213 ,  H01P1/207 ,  H01P3/12 ,  H04W88/08 ,  H05K1/11 ,  H05K1/18 ,  H05K3/34 ,  H01P1/208 ,  H01P11/00

CPC classification number: H01P1/2138 ,  H01P1/207 ,  H01P1/2088 ,  H01P3/121 ,  H01P11/007 ,  H04W88/08 ,  H05K1/115 ,  H05K1/18 ,  H05K3/3494 ,  H05K2201/015 ,  H05K2201/037 ,  H05K2201/09609 ,  H05K2201/09985

Abstract: System, apparatuses and methods are disclosed which relate to the use of substrate integrated waveguide technology in front-end modules. An example circuit card assembly for use as a cellular base station front-end is disclosed which includes at least one component printed circuit board (PCB) layer having front-end module hardware components and at least one filter PCB layer including at least one substrate integrated waveguide (SIW) filter.

公开(公告)号：US11665823B2

公开(公告)日：2023-05-30

申请号：US16875599

申请日：2020-05-15

Applicant: Ian J. Forster

Inventor： Ian J. Forster

IPC: H05K1/00 ,  H05K1/18 ,  H05K7/00 ,  H05K1/16 ,  H05K1/09 ,  H05K1/02 ,  H05K1/05 ,  H05K1/03 ,  G11C11/14 ,  H03H9/02 ,  H03H9/05

CPC classification number: H05K1/16 ,  G11C11/14 ,  H05K1/0233 ,  H05K1/034 ,  H05K1/0306 ,  H05K1/05 ,  H05K1/09 ,  H03H9/02551 ,  H03H9/02559 ,  H03H9/0542 ,  H05K2201/015 ,  H05K2201/083 ,  H05K2201/086 ,  H05K2201/10083 ,  H05K2201/10265

Abstract: A circuit device formed from a functional substrate. The circuit device comprises a functional substrate component and printed electronic elements formed on the functional substrate component. The printed electronic elements formed on the functional substrate component interact with the substrate component to perform a function and to modify the functional substrate component. The circuit device typically needs a passive base material that takes no functional part in the device operation except mechanical support.

公开(公告)号：US20180213641A1

公开(公告)日：2018-07-26

申请号：US15926014

申请日：2018-03-20

Applicant: Asahi Glass Company, Limited

Inventor： Tomoya HOSODA ,  Toru Sasaki ,  Nobutaka Kidera ,  Tatsuya Terada

IPC: H05K1/03 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/0306 ,  H05K1/0366 ,  H05K1/0393 ,  H05K1/11 ,  H05K3/0038 ,  H05K3/0047 ,  H05K3/0055 ,  H05K3/381 ,  H05K3/42 ,  H05K3/427 ,  H05K3/429 ,  H05K3/46 ,  H05K3/462 ,  H05K3/4688 ,  H05K2201/0129 ,  H05K2201/015 ,  H05K2203/095 ,  Y10T29/49165

Abstract: To produce a wiring substrate having excellent electrical characteristics with conduction failure in a hole formed in a layer made of a fluororesin material sufficiently suppressed without conducting an etching treatment using metal sodium. A process for producing a wiring substrate 1, which comprises forming a hole 20 in a laminate comprising a first conductor layer 12, a layer (A) 10 which is made of a fluororesin material containing a melt-moldable fluororesin (a) having specific functional groups and a reinforcing fiber substrate and which has a dielectric constant of from 2.0 to 3.5, a second conductor layer 14, an adhesive layer 16 and a layer (B) 18 made of a cured product of a thermosetting resin laminated in this order, applying, to an inner wall surface 20a of the hole 20, either one or both of a treatment with a permanganic acid solution and a plasma treatment without conducting an etching treatment using metal sodium, and then forming a plating layer 22 on the inner wall surface 20a of the hole 20.