公开(公告)号：US06219908B1

公开(公告)日：2001-04-24

申请号：US08975553

申请日：1997-11-20

Applicant: Warren Farnworth ,  Alan Wood

Inventor： Warren Farnworth ,  Alan Wood

IPC: H05K330

CPC classification number: H01L23/49838 ,  G01R1/0433 ,  G01R1/0466 ,  G01R1/0483 ,  G01R1/06711 ,  G01R1/0735 ,  G01R3/00 ,  G01R31/2863 ,  G01R31/287 ,  G01R31/2889 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/80 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method and apparatus for fabricating known good semiconductor dice are provided. The method includes the steps of: testing the gross functionality of dice contained on a semiconductor wafer; sawing the wafer to singulate a die; and then testing the die by assembly in a carrier having an interconnect adapted to establish electrical communication between the bond pads on the die and external test circuitry. The interconnect for the carrier can be formed using different contact technologies including: thick film contact members on a rigid substrate; self-limiting contact members on a silicon substrate; or microbump contact members with a textured surface. During assembly of the carrier, the die and interconnect are optically aligned and placed into contact with a predetermined contact force. This establishes an electrical connection between the contact members on the interconnect and the bond pads of the die. In the assembled carrier the die and interconnect are biased together by a force distribution mechanism that includes a bridge clamp, a pressure plate and a spring clip. Following testing of the die, the carrier is disassembled and the tested die is removed.

Abstract translation: 提供了一种用于制造已知的良好半导体晶片的方法和装置。 该方法包括以下步骤：测试包含在半导体晶片上的骰子的总功能; 锯切晶片以切割模具; 然后通过组装在具有适于建立管芯上的接合焊盘与外部测试电路之间的电连通的互连的载体中来测试管芯。 用于载体的互连可以使用不同的接触技术形成，包括：刚性基板上的厚膜接触构件; 硅衬底上的自限制接触构件; 或具有纹理表面的微型块接触构件。 在载体的组装期间，芯片和互连件被光学对准并且被放置成与预定的接触力接触。 这就建立了互连上的接触构件和管芯的接合垫之间的电连接。 在组装的载体中，管芯和互连件通过包括桥夹，压板和弹簧夹的力分配机构偏压在一起。 在对模具进行测试之后，拆下载体并且移除被测试的模具。

公开(公告)号：US6127736A

公开(公告)日：2000-10-03

申请号：US127652

申请日：1998-07-31

Applicant: Salman Akram

Inventor： Salman Akram

IPC: H01L21/48 ,  H01L23/498 ,  H05K1/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/14 ,  H05K3/28 ,  H05K3/32 ,  H05K3/34 ,  H05K3/40 ,  H05K3/46 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K1/113 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49827 ,  H05K3/4007 ,  H01L2224/16 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15173 ,  H01L2924/15312 ,  H01L2924/19107 ,  H05K1/0271 ,  H05K1/0306 ,  H05K2201/0133 ,  H05K2201/0154 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2203/043 ,  H05K3/143 ,  H05K3/28 ,  H05K3/325 ,  H05K3/3457 ,  H05K3/4605 ,  H05K3/4676

Abstract: A method for forming an interconnect for making a temporary or permanent electrical connection to a semiconductor dice is provided. The interconnect includes a rigid substrate on which an insulating layer and a pattern of conductors are formed. A compliant layer is formed on the insulating layer of a material such as polyimide. Vias are formed in the compliant layer with metal contacts in electrical communication with the conductors. Microbumps are formed on the compliant layer in electrical communication with the contacts and are adapted to flex with the compliant layer. The interconnect can be used to provide a temporary electrical connection for testing bare semiconductor dice. Alternately the interconnect can be used for flip chip mounting dice for fabricating multi chip modules and other electronic devices.

Abstract translation: 提供了一种用于形成用于制造与半导体裸片的暂时或永久电连接的互连的方法。 互连包括刚性基板，其上形成绝缘层和导体图案。 柔性层形成在诸如聚酰亚胺的材料的绝缘层上。 在兼容层中形成通孔，其中金属触点与导体电连通。 微胶囊形成在柔性层上，与触头电连通并且适于与柔顺层挠曲。 互连可用于提供用于测试裸半导体裸片的临时电连接。 或者，互连可以用于倒装芯片安装芯片，用于制造多芯片模块和其他电子设备。

公开(公告)号：US6127025A

公开(公告)日：2000-10-03

申请号：US21772

申请日：1998-03-10

Applicant: Anilkumar Chinuprasad Bhatt ,  Donald Herman Glatzel ,  Allen F. Moring ,  Voya Rista Markovich ,  Kostas Papathomas ,  David John Russell

Inventor： Anilkumar Chinuprasad Bhatt ,  Donald Herman Glatzel ,  Allen F. Moring ,  Voya Rista Markovich ,  Kostas Papathomas ,  David John Russell

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/02 ,  H05K3/24 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  B32B15/00

CPC classification number: H05K3/4652 ,  H05K1/113 ,  H05K3/4069 ,  H05K3/4602 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2924/12044 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/092 ,  H05K2201/0959 ,  H05K2203/0191 ,  H05K2203/025 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/0554 ,  H05K3/0023 ,  H05K3/0094 ,  H05K3/025 ,  H05K3/246 ,  H05K3/429 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/24942 ,  Y10T428/249996

Abstract: Circuit boards are manufactured by forming a substrate with a dielectric surface, laminating a metal foil and a peelable film to the substrate, and forming holes in the substrate through the peelable film and foil. A filler material with an organic base may be filled with electroconductive particles or dielectric thermoconductive particles. The filler material is deposited onto a sacrificial carrier and the filler material is heated to at least partially cure it. The filler material is laminated onto the peelable film with sufficient heat and pressure to force the filler material to fill the holes. For thermoconductive filler the holes are filled sufficient for electrical connection through the holes. The peelable layer, sacrificial carrier and filler material remaining therebetween are peeled off the copper foil. The filler material is abraded to the level of the foil and is then copper plated. The copper is patterned to form a wiring layer. A permanent dielectric photoresist layer is formed over the wiring layer and via holes are formed through the photoimagable dielectric over pads and conductors of the wiring layer. Holes are formed through the substrate and the photoimagable dielectric, walls of the via holes, and walls of the through holes are copper plated. The copper plating on the photoimagable dielectric is patterned to form an exterior wiring layer which is covered by solder resist with windows over lands around the through holes and surface mount connection pads of the exterior wiring layer to form a high density circuitized substrate. Surface mount components and/or pin in hole components are attached to the circuitized substrate with solder joints between terminals of the components and the lands and/or connection pads to form a high density circuit board assembly. One or more of the circuit board assemblies are mounted in an enclosure with a power supply, CPU, RAM, and I/O means to form an improved information handling system with increased performance due to shorter signal flight times due to the high component density.

公开(公告)号：US6036836A

公开(公告)日：2000-03-14

申请号：US994805

申请日：1997-12-19

Applicant: Joris Antonia Franciscus Peeters ,  Louis Joseph Vandam ,  Koenraad Juliaan Georges Allaert ,  Ann Marie Ackaert ,  Andre Michel Van Calster ,  Maria Eugenie Andre Vereeken ,  Suixin Zhang ,  Johan De Baets ,  Bart Leo Alfons Maurice Vandevelde

Inventor： Joris Antonia Franciscus Peeters ,  Louis Joseph Vandam ,  Koenraad Juliaan Georges Allaert ,  Ann Marie Ackaert ,  Andre Michel Van Calster ,  Maria Eugenie Andre Vereeken ,  Suixin Zhang ,  Johan De Baets ,  Bart Leo Alfons Maurice Vandevelde

IPC: H01L21/48 ,  H01L23/12 ,  H01L23/498 ,  H05K1/11 ,  H05K3/00 ,  H05K3/06 ,  H05K3/10 ,  H05K3/24 ,  H05K3/28 ,  H05K3/40 ,  H05K3/42 ,  C25D5/02

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L23/49811 ,  H05K3/243 ,  H01L2924/0002 ,  H05K1/114 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2203/0361 ,  H05K2203/072 ,  H05K3/0094 ,  H05K3/062 ,  H05K3/108 ,  H05K3/28 ,  H05K3/427

Abstract: A process to create metallic stand-offs or studs on a printed circuit board (PCB). The process allows to obtain studs constituted by three successive layers of metal (Cu1, Cu2 and Cu3 or Ni) of which at least the two first layers are made of copper. The height of the so-created stand-off is sufficient to use it in the flip chip technology to assemble chips to a printed circuit board. The present process is implemented according either to the electro-plating (galvano-plating) or to the electrochemical-plating technique.

Abstract translation: 在印刷电路板（PCB）上创建金属支座或螺柱的工艺。 该方法允许获得由三个连续的金属层（Cu1，Cu2和Cu3或Ni）构成的柱，其中至少两个第一层由铜制成。 如此设计的支座的高度足以在倒装芯片技术中将芯片组装到印刷电路板上。 本方法根据电镀（电镀法）或电镀法进行。

公开(公告)号：US6020624A

公开(公告)日：2000-02-01

申请号：US53273

申请日：1998-04-01

Applicant: Alan G. Wood ,  Salman Akram ,  Warren M. Farnworth

Inventor： Alan G. Wood ,  Salman Akram ,  Warren M. Farnworth

IPC: G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L21/68 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  H01L29/06 ,  H01L23/02 ,  H01L23/28

CPC classification number: H05K3/4007 ,  G01R1/0466 ,  G01R1/0483 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/80 ,  H01L24/85 ,  G01R1/06738 ,  G01R1/0735 ,  G01R3/00 ,  G01R31/2831 ,  G01R31/2863 ,  H01L2224/16145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/73207 ,  H01L2224/85001 ,  H01L2224/85205 ,  H01L2225/06562 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/423

Abstract: A method for forming an interconnect for semiconductor devices is provided. The interconnect includes raised contact structures covered with a conductive layer and having penetrating projections for penetrating contacts for the semiconductor devices. In an illustrative embodiment, the interconnect can be used to form a bi-substrate die. An interconnect substrate for the bi-substrate die includes control and logic circuitry and a memory substrate for the bi-substrate die includes a memory array. The interconnect can also be used to establish an electrical connection to microscopic contacts formed on a conventional die. In addition, the interconnect can be formed with three dimensional micro structures for contacting the microscopic contacts. Still further, the interconnect can be formed as wafer interconnect for electrically contacting dice contained on a wafer or for stacking multiple wafers.

Abstract translation: 提供一种用于形成用于半导体器件的互连的方法。 互连包括被导电层覆盖的凸起的接触结构，并且具有用于穿透用于半导体器件的触点的穿透突起。 在说明性实施例中，互连可用于形成双衬底裸片。 用于双衬底裸片的互连衬底包括控制和逻辑电路，并且用于双衬底裸片的存储器衬底包括存储器阵列。 互连还可用于建立与常规裸片上形成的微观触点的电连接。 此外，互连可以由用于接触微观触点的三维微结构形成。 此外，互连可以形成为用于电接触包含在晶片上的骰子或用于堆叠多个晶片的晶片互连。

公开(公告)号：US6011310A

公开(公告)日：2000-01-04

申请号：US722321

申请日：1996-09-27

Applicant: Toshiki Naito ,  Kazuo Ouchi

Inventor： Toshiki Naito ,  Kazuo Ouchi

IPC: H01L21/60 ,  H01L23/498 ,  H01L23/50 ,  H05K3/40 ,  H05K3/42 ,  H01L23/48 ,  H01L23/053 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/81 ,  H01L23/4985 ,  H05K3/4007 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/1572 ,  H05K3/423

Abstract: Disclosed are a film carrier comprising an insulating layer having laid therein an electrically conductive circuit such that the circuit is not exposed on the surface thereof, wherein conductive passages from the conductive circuit to one surface of the insulating layer are formed in the insulating layer and via holes from said conductive circuit to the other surface of the insulating layer are formed and a semiconductor device prepared by mounting a semiconductor element on the insulating layer of the film carrier. The film carrier can sufficiently correspond to pitch-fining and high-density mounting of a semiconductor element wiring, can surely perform the connecting operation of inner lead bonding and outer lead bonding and gives the mounting area of as small as possible.

Abstract translation: 公开了一种薄膜载体，其包括绝缘层，其中放置有导电电路，使得该电路不在其表面上露出，其中从导电电路到绝缘层的一个表面的导电通道形成在绝缘层中，并且经由 形成从所述导电电路到绝缘层的另一表面的孔，以及通过将半导体元件安装在膜载体的绝缘层上而制备的半导体器件。 薄膜载体可以充分地对应于半导体元件布线的节距精细和高密度安装，可以可靠地执行内引线接合和外引线接合的连接操作，并且使安装面积尽可能小。

公开(公告)号：US6000129A

公开(公告)日：1999-12-14

申请号：US41845

申请日：1998-03-12

Applicant: Anilkumar Chinuprasad Bhatt ,  Donald Herman Glatzel ,  Allen F. Moring ,  Voya Rista Markovich ,  Kostas Papathomas ,  David John Russell

Inventor： Anilkumar Chinuprasad Bhatt ,  Donald Herman Glatzel ,  Allen F. Moring ,  Voya Rista Markovich ,  Kostas Papathomas ,  David John Russell

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/02 ,  H05K3/24 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H01K3/10

CPC classification number: H05K3/4652 ,  H05K1/113 ,  H05K3/4069 ,  H05K3/4602 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2924/12044 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/092 ,  H05K2201/0959 ,  H05K2203/0191 ,  H05K2203/025 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/0554 ,  H05K3/0023 ,  H05K3/0094 ,  H05K3/025 ,  H05K3/246 ,  H05K3/429 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/24942 ,  Y10T428/249996

Abstract: Circuit boards are manufactured by forming a substrate with a dielectric surface, laminating a metal foil to the substrate, and forming holes in the substrate through the foil. A filler material with an organic base may be filled with electroconductive particles or dielectric thermoconductive particles. The filler material is deposited into the holes and is heated to at least partially cure it. The surface of the filler material is seeded and electrolessly plated to form a conductive coating on the metal foil and the filler material. The coating is then patterned to form a wiring layer. A second set of holes may be formed in the circuitized substrate after the hole filling step, which are also electrolessly plated.

Abstract translation: 电路板通过形成具有电介质表面的基板，将金属箔层压到基板上，并通过箔形成在基板中的孔来制造。 具有有机基底的填充材料可以填充有导电颗粒或介电导热颗粒。 填充材料沉积到孔中并被加热至少部分地固化。 填充材料的表面接种并化学镀，以在金属箔和填料上形成导电涂层。 然后将涂层图案化以形成布线层。 可以在孔填充步骤之后的电路化基板中形成第二组孔，其也是无电镀的。

公开(公告)号：US5956843A

公开(公告)日：1999-09-28

申请号：US795182

申请日：1997-02-04

Applicant: Shogo Mizumoto ,  Yutaka Tsukada

Inventor： Shogo Mizumoto ,  Yutaka Tsukada

IPC: H05K3/40 ,  H05K1/11 ,  H05K3/00 ,  H05K3/10 ,  H05K3/42 ,  H05K3/46 ,  H05K3/38

CPC classification number: H05K1/113 ,  H05K3/421 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/025 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/4069 ,  H05K3/423 ,  H05K3/4644 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49167 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: A multilayered printed wiring board includes two or more layers each having a via hole therein, these holes aligned vertically above one another to minimize board real estate while assuring an effective circuit path between respective points on the two layers. One or both via holes can be filled with either an electrically conductive material (e.g., copper paste) or a nonconductive material (e.g., resin).

Abstract translation: 多层印刷电路板包括两层或更多层，每层具有通孔，这些孔彼此垂直排列，以最小化板的空间，同时确保两层各点之间的有效电路路径。 一个或两个通孔可以用导电材料（例如铜膏）或非导电材料（例如树脂）填充。

公开(公告)号：US5930890A

公开(公告)日：1999-08-03

申请号：US858192

申请日：1997-04-21

Applicant: William T. Chou ,  Solomon I. Beilin ,  David A. Horine ,  David Kudzuma ,  Michael G. Lee ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

Inventor： William T. Chou ,  Solomon I. Beilin ,  David A. Horine ,  David Kudzuma ,  Michael G. Lee ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

IPC: G03F7/26 ,  H01L21/48 ,  H01L23/12 ,  H01L23/52 ,  H05K3/18 ,  H05K3/40 ,  H01K3/10

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L2924/00013 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2203/0577 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204

Abstract: An interconnecting post for mounting a microelectronic device such as an integral circuit chip is fabricated with generally uniform cross-section, by forming a first layer of positive photoresist on a substrate, soft-baking that first layer and exposing it for a short time with a wide-apertured mask or simply a UV blank flood exposure. Without developing the first layer, a second layer of positive resist is then applied over the first layer, soft-baked, and then exposed with a narrow-apertured mask. During the soft-baking of the second layer, some of its activator in the photoresist compound diffuses into the exposed portion of the first layer and modifies its solubility in such a way that, when the layers are subsequently developed, the developer partially undercuts the unexposed portion of the first layer to form in the photoresist an opening of generally uniform cross-section. This opening can then be filled by plating to produce a strong, integral interconnect post.

Abstract translation: 通过在基板上形成第一层正性光致抗蚀剂，通过在第一层上软化烘烤该第一层并将其暴露在短时间内，用一个整体电路芯片来形成用于安装诸如集成电路芯片的微电子器件的互连柱， 宽孔径面罩或简单的UV空白洪水曝光。 在不显影第一层的情况下，将第二层正性抗蚀剂涂覆在第一层上，软化，然后用窄孔径掩模曝光。 在第二层的软烘烤期间，光致抗蚀剂化合物中的一些活化剂扩散到第一层的暴露部分，并以这样的方式改变其溶解度，使得当这些层随后显影时，显影剂部分地削弱未曝光 第一层的部分以在光致抗蚀剂中形成具有大致均匀横截面的开口。 然后可以通过电镀填充该开口以产生强大的整体互连柱。

公开(公告)号：US5904499A

公开(公告)日：1999-05-18

申请号：US906045

申请日：1997-08-05

Applicant: Benedict G Pace

Inventor： Benedict G Pace

IPC: H01L21/48 ,  H01L21/60 ,  H01L23/053 ,  H01L23/14 ,  H01L23/15 ,  H01L23/34 ,  H01L23/433 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H05K1/03 ,  H05K3/40 ,  H05K3/46 ,  H01L21/44

CPC classification number: H01L24/81 ,  H01L21/485 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/053 ,  H01L23/147 ,  H01L23/15 ,  H01L23/34 ,  H01L23/4334 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L23/5382 ,  H01L24/97 ,  H05K3/4007 ,  H01L2224/1147 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L24/45 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K3/4644

Abstract: An electronic packaging module for bonding of power semiconductor devices is produced. The semiconductor device is mounted on a base, and enclosed by a frame and lid. The lid is an insulating substrate having a conductive pattern with protuberances on the conductive pattern of the substrate. The protuberances are of a soft, ductile metal capable of being metallurgically bonded to the metallization pads of semiconductor devices. The metal protuberances are bonded to the semiconductor device joining it to the lid, and through the conductive pattern of the lid connecting the device to the input/output contacts of the package.

Abstract translation: 制造用于功率半导体器件的接合的电子封装模块。 半导体器件安装在基座上，并被框架和盖子包围。 盖是具有在基板的导电图案上的突起的导电图案的绝缘基板。 该突起具有能够与半导体器件的金属化焊盘冶金结合的柔软的韧性金属。 金属突起结合到连接到盖的半导体器件，并且通过将器件的导体图案连接到封装的输入/输出触点。