公开(公告)号：US20240162401A1

公开(公告)日：2024-05-16

申请号：US18078103

申请日：2022-12-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chuan-Lan Lin ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Chun-Ting Yeh

IPC: H01L33/62 ,  H01L25/075

CPC classification number: H01L33/62 ,  H01L25/0753 ,  H01L2933/0066

Abstract: A method for fabricating a micro display device includes the steps of providing a wafer comprising a first area, a second area, and a third area, forming first bonding pads on the first area, forming second bonding pads on the second area, and forming third bonding pads on the third area. Preferably, the first bonding pads and the second bonding pads are made of different materials and the first bonding pads and the third bonding pads are made of different materials.

公开(公告)号：US20240162313A1

公开(公告)日：2024-05-16

申请号：US18416764

申请日：2024-01-18

Applicant: UNITED MICROLETRONICS CORP.

Inventor： Chih-Tung Yeh ,  Chun-Liang Hou ,  Wen-Jung Liao ,  Chun-Ming Chang ,  Yi-Shan Hsu ,  Ruey-Chyr Lee

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/4175 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/0684

Abstract: A method for forming a high electron mobility transistor is disclosed. A mesa structure having a channel layer and a barrier layer is formed on a substrate. The mesa structure has two first edges extending along a first direction and two second edges extending along a second direction. A passivation layer is formed on the substrate and the mesa structure. A first opening and a plurality of second openings connected to a bottom surface of the first opening are formed and through the passivation layer, the barrier layer and a portion of the channel layer. In a top view, the first opening exposes the two first edges of the mesa structure without exposing the two second edges of the mesa structure. A metal layer is formed in the first opening and the second openings thereby forming a contact structure.

公开(公告)号：US20240162093A1

公开(公告)日：2024-05-16

申请号：US18080688

申请日：2022-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chu-Chun Chang ,  Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/823456 ,  H01L27/088 ,  H01L29/42376 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device includes first providing a substrate having a core region, a LNA region, a I/O region, and a PA region, forming a first gate structure on the LNA region, a second gate structure on the PA region, a third gate structure on the core region, and a fourth gate structure on the I/O region, forming an interlayer dielectric (ILD) layer on the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure, and then forming a first hard mask on the first gate structure and a second hard mask on the second gate structure. Preferably, a width of the first hard mask is greater than a width of the first gate structure.

公开(公告)号：US11984442B2

公开(公告)日：2024-05-14

申请号：US17715974

申请日：2022-04-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ruei-Yau Chen ,  Wei-Jen Wang ,  Kun-Yuan Wu ,  Chien-Fu Chen ,  Chen-Hsien Hsu

IPC: H01L27/02

CPC classification number: H01L27/0207

Abstract: A layout includes a first and a second standard cells abutting along a boundary line. The first cell includes first fins. An edge of the first fins closest to and away from the boundary line by a distance D1. A first gate line over-crossing the first fins protrudes from the edge by a length L1. The second cell includes second fins. An edge of the second fins closest to and away from the boundary line by a distance D2. A second gate line over-crossing the second fins protrudes from the edge by a length L2. Two first dummy gate lines at two sides of the first fins and two second dummy lines at two sides of the second fins are respectively away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1≤D1−S, L2≤D2−S, and D1≠D2.

公开(公告)号：US20240154512A1

公开(公告)日：2024-05-09

申请号：US18081706

申请日：2022-12-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiu-Ming Yeh ,  Min-Chia Wang

IPC: H02M1/00 ,  H02M3/155

CPC classification number: H02M1/0003 ,  H02M3/155

Abstract: A current generator includes a startup circuit and a bandgap reference circuit coupled to the startup circuit. The startup circuit is for generating a first voltage. The bandgap reference circuit is for generating a second voltage. The bandgap reference circuit includes an operational amplifier. The operational amplifier includes a bias source circuit and a bias generator circuit. The bias source circuit is for generating a reference current according to the first voltage and the second voltage. The bias generator circuit is for generating bias voltages according to the reference current. The startup circuit and the bandgap reference circuit receive a supply voltage.

公开(公告)号：US11977367B2

公开(公告)日：2024-05-07

申请号：US17318199

申请日：2021-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chi Lin ,  Li-Hsin Yang ,  Yu-Shan Hsu

IPC: G05B19/418 ,  G06F3/048 ,  G06F3/04842 ,  G06F8/33 ,  G06F8/34 ,  G06F8/40

CPC classification number: G05B19/41835 ,  G05B19/41865 ,  G06F3/048 ,  G06F3/04842 ,  G06F8/33 ,  G06F8/34 ,  G06F8/40 ,  G05B2219/2206 ,  G05B2219/23121 ,  G05B2219/23135 ,  G05B2219/23158

Abstract: A command script editing method, a command script editor and a graphic user interface are provided. The command script editing method includes the following steps. The command node is edited according to at least one inputting action or at least one image identifying action performed on the operation frame when the command script editor is at an image editing mode. The command node is edited according to a setting content of at least one process action when the command script editor is at a process editing mode.

公开(公告)号：US20240145594A1

公开(公告)日：2024-05-02

申请号：US17993983

申请日：2022-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7846 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for fabricating semiconductor device includes the steps of first forming a shallow trench isolation (STI) in a substrate, forming a gate structure on the STI and the substrate, forming a patterned mask on the STI and the gate structure, performing an etching process to remove part of the STI for forming a first trench adjacent to one side of the gate structure and a second trench adjacent to another side of the gate structure, and then forming a contact etch stop layer (CESL) on the gate structure and into the first trench and the second trench.

公开(公告)号：US20240145412A1

公开(公告)日：2024-05-02

申请号：US17994382

申请日：2022-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Che Huang ,  Chao-Ting Chen ,  Jui-Fa Lu ,  Chi-Heng Lin

IPC: H01L23/60 ,  H01L23/522

CPC classification number: H01L23/60 ,  H01L23/5221 ,  H01L23/5226

Abstract: A semiconductor device includes a logic circuit region having at least one core device and at least one input/output (I/O) device. The at least one core device has a first accumulative antenna ratio, and the at least one I/O device has a second accumulative antenna ratio. The first accumulative antenna ratio is greater than the second accumulative antenna ratio.

公开(公告)号：US20240136423A1

公开(公告)日：2024-04-25

申请号：US18395657

申请日：2023-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Che-Hung Huang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/66 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/7786

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.

公开(公告)号：US20240136312A1

公开(公告)日：2024-04-25

申请号：US17989633

申请日：2022-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Ching-Yang Wen ,  XINGXING CHEN

IPC: H01L23/00 ,  H01L25/16 ,  H01L27/12 ,  H01L49/02

CPC classification number: H01L24/08 ,  H01L24/16 ,  H01L25/16 ,  H01L27/1203 ,  H01L28/90 ,  H01L2224/08145 ,  H01L2224/16227

Abstract: A semiconductor device includes a first wafer having a deep trench capacitor and a second wafer bonded to the first wafer, in which the second wafer includes a first active device on a first silicon-on-insulator (SOI) substrate and a first metal interconnection connected to the first active device and the deep trench capacitor. The first wafer further includes the deep trench capacitor disposed in a substrate, a first inter-layer dielectric (ILD) layer on the deep trench capacitor, a first inter-metal dielectric (IMD) layer on the first ILD layer, and a second metal interconnection in the first ILD layer and the first IMD layer.