公开(公告)号：US10971224B2

公开(公告)日：2021-04-06

申请号：US16886330

申请日：2020-05-28

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Chang Hua Siau

IPC: G11C11/00 ,  G11C13/00 ,  G11C8/08 ,  G11C8/10 ,  H03K3/356 ,  H03K19/0185

Abstract: A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.

公开(公告)号：US20200335144A1

公开(公告)日：2020-10-22

申请号：US16869816

申请日：2020-05-08

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Seow Fong Lim ,  Chang Hua Siau

IPC: G11C7/22 ,  G11C5/02 ,  G11C11/21 ,  G11C13/00 ,  G11C8/10 ,  G11C8/12

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

公开(公告)号：US20200303005A1

公开(公告)日：2020-09-24

申请号：US16838423

申请日：2020-04-02

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Chang Hua Siau

IPC: G11C13/00 ,  G11C11/21

Abstract: Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.

公开(公告)号：US20200272343A1

公开(公告)日：2020-08-27

申请号：US16811401

申请日：2020-03-06

Applicant: Unity Semiconductor Corporation

Inventor： Chang Hua Siau

IPC: G06F3/06 ,  G11C8/08 ,  G11C11/419 ,  G11C13/00 ,  G11C5/06

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.

公开(公告)号：US20200251167A1

公开(公告)日：2020-08-06

申请号：US16784332

申请日：2020-02-07

Applicant: Unity Semiconductor Corporation

Inventor： Chang Hua Siau ,  Bruce Lynn Bateman

IPC: G11C13/00 ,  H01L27/10 ,  G11C5/06 ,  G11C7/18 ,  G11C5/08 ,  G11C7/12 ,  G11C16/24 ,  G11C7/00 ,  G11C7/04

Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

公开(公告)号：US10672467B2

公开(公告)日：2020-06-02

申请号：US16460708

申请日：2019-07-02

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Chang Hua Siau

IPC: G11C11/00 ,  G11C13/00 ,  G11C8/08 ,  G11C8/10 ,  H03K3/356 ,  H03K19/0185

Abstract: A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.

公开(公告)号：US10585603B2

公开(公告)日：2020-03-10

申请号：US16018837

申请日：2018-06-26

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Chang Hua Siau

IPC: G11C11/00 ,  G06F3/06 ,  G11C8/08 ,  G11C11/419 ,  G11C13/00 ,  G11C5/06

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.

公开(公告)号：US10566056B2

公开(公告)日：2020-02-18

申请号：US16297303

申请日：2019-03-08

Applicant: Unity Semiconductor Corporation

Inventor： Chang Hua Siau ,  Bruce Lynn Bateman

IPC: G11C11/00 ,  G11C13/00 ,  G11C7/04 ,  G11C7/00 ,  G11C16/24 ,  G11C7/12 ,  G11C5/08 ,  G11C7/18 ,  G11C5/06

Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

公开(公告)号：US20200013460A1

公开(公告)日：2020-01-09

申请号：US16511205

申请日：2019-07-15

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Chang Hua Siau

IPC: G11C13/00 ,  G11C11/21

Abstract: Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.

公开(公告)号：US10529778B2

公开(公告)日：2020-01-07

申请号：US16042359

申请日：2018-07-23

Applicant: Unity Semiconductor Corporation

Inventor： Lidia Vereen ,  Bruce L. Bateman ,  David A. Eggleston ,  Louis C. Parrillo

IPC: H01L21/20 ,  H01L27/24 ,  H01L45/00 ,  H01L23/528

Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.