公开(公告)号：US09324610B2

公开(公告)日：2016-04-26

申请号：US14455939

申请日：2014-08-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Ching-Ling Lin ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chun-Hsien Lin

IPC: H01L21/02 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/665 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one metal gate thereon, a source/drain region adjacent to two sides of the at least one metal gate, and an interlayer dielectric (ILD) layer around the at least one metal gate; forming a plurality of contact holes in the ILD layer to expose the source/drain region; forming a first metal layer in the contact holes; performing a first thermal treatment process; and performing a second thermal treatment process.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有至少一个金属栅极的衬底，与所述至少一个金属栅极的两侧相邻的源极/漏极区域以及围绕所述至少一个金属栅极的层间电介质层 ; 在所述ILD层中形成多个接触孔以暴露所述源/漏区; 在所述接触孔中形成第一金属层; 执行第一热处理过程; 并执行第二热处理过程。

公开(公告)号：US20160071844A1

公开(公告)日：2016-03-10

申请号：US14512475

申请日：2014-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jiun Shen ,  Ssu-I Fu ,  Yen-Liang Wu ,  Chia-Jong Liu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Man-Ling Lu ,  Yi-Wei Chen

IPC: H01L27/088 ,  H01L21/308 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/8236

CPC classification number: H01L21/308 ,  H01L21/02238 ,  H01L21/30604 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66818

Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.

Abstract translation: 鳍状结构包括具有位于第一区域中的第一鳍状结构的基板和位于第二区域中的第二鳍状结构，其中第二鳍状结构包括梯形横截面轮廓部分 。 本发明还提供了形成该鳍状结构的两种方法。 在一种情况下，提供具有第一鳍状结构和第二鳍状结构的基板。 执行处理工艺以改变第二鳍状结构的顶部的外表面，从而形成修改部分。 进行去除处理以通过对第一鳍状结构和第二鳍状结构以及改性部分的高去除选择性去除改性部分，由此第二鳍状结构具有梯形横截面 形成轮廓部分。

公开(公告)号：US20160071800A1

公开(公告)日：2016-03-10

申请号：US14513230

申请日：2014-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chia Chang Hsu ,  Hsin-Fu Huang ,  Chun-Yuan Wu ,  Shih-Fang Tzou

IPC: H01L23/535 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure including a dielectric layer, a titanium layer, a titanium nitride layer and a metal is provided. The dielectric layer is disposed on a substrate, wherein the dielectric layer has a via. The titanium layer covers the via, wherein the titanium layer has tensile stress lower than 1500 Mpa. The titanium nitride layer conformally covers the titanium layer. The metal fills the via. The present invention also provides a semiconductor process for forming said semiconductor structure. The semiconductor process includes the following steps. A dielectric layer is formed on a substrate, wherein the dielectric has a via. A titanium layer conformally covers the via, wherein the titanium layer has compressive stress lower than 500 Mpa. A titanium nitride layer is formed to conformally cover the titanium layer. A metal fills the via.

Abstract translation: 提供了包括电介质层，钛层，氮化钛层和金属的半导体结构。 电介质层设置在基板上，其中介电层具有通孔。 钛层覆盖通孔，其中钛层具有低于1500Mpa的拉伸应力。 氮化钛层共形地覆盖钛层。 金属填充通孔。 本发明还提供了一种用于形成所述半导体结构的半导体工艺。 半导体工艺包括以下步骤。 介电层形成在基板上，其中电介质具有通孔。 钛层保形地覆盖通孔，其中钛层具有低于500Mpa的压应力。 形成氮化钛层以保形地覆盖钛层。 金属填充通孔。

公开(公告)号：US20160049496A1

公开(公告)日：2016-02-18

申请号：US14495907

申请日：2014-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Man-Ling Lu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Wen-Jiun Shen ,  Chia-Jong Liu ,  Ssu-I Fu ,  Yi-Wei Chen

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/66553 ,  H01L21/02057 ,  H01L21/0217 ,  H01L21/3086 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78

Abstract: A MOS transistor including a gate structure, an epitaxial spacer and an epitaxial structure is provided. The gate structure is disposed on a substrate. The epitaxial spacer is disposed on the substrate besides the gate structure, wherein the epitaxial spacer includes silicon and nitrogen, and the ratio of nitrogen to silicon is larger than 1.3. The epitaxial structure is disposed in the substrate besides the epitaxial spacer. A semiconductor process includes the following steps for forming an epitaxial structure. A gate structure is formed on a substrate. An epitaxial spacer is formed on the substrate besides the gate structure for defining the position of an epitaxial structure, wherein the epitaxial spacer includes silicon and nitrogen, and the ratio of nitrogen to silicon is larger than 1.3. The epitaxial structure is formed in the substrate besides the epitaxial spacer.

Abstract translation: 提供了包括栅极结构，外延隔离物和外延结构的MOS晶体管。 栅极结构设置在基板上。 除了栅极结构之外，外延衬垫设置在衬底上，其中外延衬垫包括硅和氮，并且氮与硅之比大于1.3。 外延结构除了外延间隔物之外还设置在基板中。 半导体工艺包括用于形成外延结构的以下步骤。 在基板上形成栅极结构。 除了用于限定外延结构的位置的栅极结构之外，在衬底上形成外延衬垫，其中外延衬垫包括硅和氮，并且氮与硅之比大于1.3。 该外延结构除了外延间隔物外还形成在基板中。

公开(公告)号：US20160027892A1

公开(公告)日：2016-01-28

申请号：US14852624

申请日：2015-09-13

Applicant: United Microelectronics Corp.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Yi-Wei Chen ,  Shi-Xiong Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Hsiao-Pang Chou ,  Chia-Lin Lu

IPC: H01L29/49 ,  H01L29/423 ,  H01L27/088

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/088 ,  H01L29/4232 ,  H01L29/517 ,  H01L29/66545

Abstract: The metal gate structure includes at least a substrate, a dielectric layer, first and second trenches, first metal layer and second metal layers, and two cap layers. In particular, the dielectric layer is disposed on the substrate, and the first and second trenches are disposed in the dielectric layer. The width of the first trench is less than the width of the second trench. The first and second metal layers are respectively disposed in the first trench and the second trench, and the height of the first metal layer is less than or equal to the height of the second metal layer. The cap layers are respectively disposed in a top surface of the first metal layer and a top surface of the second metal layer.

Abstract translation: 金属栅极结构至少包括衬底，电介质层，第一和第二沟槽，第一金属层和第二金属层以及两个盖层。 特别地，介电层设置在基板上，并且第一和第二沟槽设置在电介质层中。 第一沟槽的宽度小于第二沟槽的宽度。 第一和第二金属层分别设置在第一沟槽和第二沟槽中，第一金属层的高度小于或等于第二金属层的高度。 盖层分别设置在第一金属层的顶表面和第二金属层的顶表面中。

公开(公告)号：US09209273B1

公开(公告)日：2015-12-08

申请号：US14463677

申请日：2014-08-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Yi-Wei Chen ,  Shi-Xiong Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Hsiao-Pang Chou ,  Chia-Lin Lu

IPC: H01L21/4763 ,  H01L29/66 ,  H01L27/088 ,  H01L29/51 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/088 ,  H01L29/4232 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating a metal gate structure includes providing a substrate on which a dielectric layer, a first trench disposed in the dielectric layer, a first metal layer filling up the first trench, a second trench disposed in the dielectric layer, a second metal layer filling up the second trench are disposed, and the width of the first trench is less than the width of the second trench; forming a mask layer to completely cover the second trench; performing a first etching process to remove portions of the first metal layer when the second trench is covered by the mask layer; and performing a second etching process to concurrently remove portions of the first metal layer and portions of the second metal layer after the first etching process.

Abstract translation: 一种用于制造金属栅极结构的方法，包括：提供基板，其上布置介电层，设置在电介质层中的第一沟槽，填充第一沟槽的第一金属层，设置在电介质层中的第二沟槽，第二金属层 设置填充第二沟槽，并且第一沟槽的宽度小于第二沟槽的宽度; 形成掩模层以完全覆盖所述第二沟槽; 当所述第二沟槽被所述掩模层覆盖时，执行第一蚀刻工艺以去除所述第一金属层的部分; 以及执行第二蚀刻工艺，以在第一蚀刻工艺之后同时去除第一金属层的部分和第二金属层的部分。

公开(公告)号：US20140038374A1

公开(公告)日：2014-02-06

申请号：US14060568

申请日：2013-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Wei Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Jei-Ming Chen ,  Tsai-Fu Hsiao

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7843

Abstract: A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.

Abstract translation: 公开了一种CMOS晶体管及其制造方法。 提供了至少具有PMOS晶体管和NMOS晶体管的半导体衬底。 PMOS晶体管的源极/漏极包括SiGe外延层。 执行碳注入工艺以在PMOS晶体管的源极/漏极的顶部部分中形成碳掺杂层。 在源极/漏极上形成硅化物层。 在PMOS晶体管和NMOS晶体管上形成CESL。 碳掺杂层的形成能够防止Ge扩散。