公开(公告)号：US20240113215A1

公开(公告)日：2024-04-04

申请号：US17980538

申请日：2022-11-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/311 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/022 ,  H01L21/31111 ,  H01L21/31144 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/42316 ,  H01L29/66462

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a channel layer on a substrate, forming a first barrier layer on the channel layer, forming a p-type semiconductor layer on the first barrier layer, forming a first patterned passivation layer on the p-type semiconductor layer, and then forming a gate electrode on the first patterned passivation layer. Preferably, the gate electrode includes a first portion adjacent to one side of the first patterned passivation layer and a second portion adjacent to another side of the first patterned passivation layer.

公开(公告)号：US20240107895A1

公开(公告)日：2024-03-28

申请号：US18528707

申请日：2023-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Jian-Cheng Chen ,  Yu-Ping Wang ,  Yu-Ruei Chen

IPC: H10N50/80 ,  G11C11/16 ,  H01L27/02 ,  H10B61/00

CPC classification number: H10N50/80 ,  G11C11/161 ,  H01L27/0207 ,  H10B61/22

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

公开(公告)号：US20240107777A1

公开(公告)日：2024-03-28

申请号：US17964935

申请日：2022-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Hung-Chan Lin ,  Chung-Yi Chiu

IPC: H01L27/22 ,  H01L43/04 ,  H01L43/06 ,  H01L43/14

CPC classification number: H01L27/228 ,  H01L43/04 ,  H01L43/06 ,  H01L43/14

Abstract: An SOT MRAM structure includes a word line. A second source/drain doping region and a fourth source/drain doping region are disposed at the same side of the word line. A first conductive line contacts the second source/drain doping region. A second conductive line contacts the fourth source/drain doping region. The second conductive line includes a third metal pad. A memory element contacts an end of the first conductive line. A second SOT element covers and contacts a top surface of the memory element. The third metal pad covers and contacts part of the top surface of the second SOT element.

公开(公告)号：US20240105720A1

公开(公告)日：2024-03-28

申请号：US18525909

申请日：2023-12-01

Applicant: United Microelectronics Corp.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L27/088 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/308 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66545 ,  H01L29/66818 ,  H01L21/845

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.

公开(公告)号：US20240105502A1

公开(公告)日：2024-03-28

申请号：US18537861

申请日：2023-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Tsai HUNG ,  Yi LIU ,  Guo-Hai ZHANG ,  Ching-Hwa TEY

IPC: H01L21/762 ,  H01L23/00 ,  H01L27/12

CPC classification number: H01L21/76251 ,  H01L23/562 ,  H01L23/564 ,  H01L27/1203

Abstract: A semiconductor structure is provided. The semiconductor structure includes a wafer structure. The wafer structure has a normal region and a trimmed region adjacent to the normal region. A top surface of the trimmed region is lower than a top surface of the normal region. The semiconductor structure includes a dielectric layer and a conductive layer disposed on the wafer structure in the normal region and the trimmed region. The semiconductor structure includes a protective layer disposed on a portion of the dielectric layer in the trimmed region and a portion of the conductive layer in the trimmed region. The semiconductor structure includes another dielectric layer disposed on a portion of the dielectric layer in the normal region and a portion of the conductive layer in the normal region and on the protective layer.

公开(公告)号：US11943911B2

公开(公告)日：2024-03-26

申请号：US16102715

申请日：2018-08-13

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yukihiro Nagai

IPC: H10B12/00

CPC classification number: H10B12/09 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/50

Abstract: A semiconductor structure for a memory device includes a substrate including a memory cell region and a peripheral circuit region defined thereon, at least an active region formed in the peripheral circuit region, a buried gate structure formed in the active region in the peripheral circuit region, a conductive line structure formed on the buried gate structure, and at least a bit line contact plug formed in the memory cell region.

公开(公告)号：US11935788B2

公开(公告)日：2024-03-19

申请号：US17137298

申请日：2020-12-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L23/544 ,  H01L21/78

CPC classification number: H01L21/78 ,  H01L23/544

Abstract: A manufacturing method of a semiconductor device includes the following steps. A singulation process is performed to a semiconductor wafer for forming semiconductor dies and includes a first cutting step, a thinning step, and a second cutting step. The first cutting step is configured to form first openings in the semiconductor wafer by etching. A portion of the semiconductor wafer is located between each first opening and a back surface and removed by the thinning step. Each first opening penetrates through the semiconductor wafer after the thinning step. The second cutting step is configured to form second openings. Each second opening penetrates through the semiconductor wafer for separating the semiconductor dies. A semiconductor die includes two first side surfaces opposite to each other and two second side surfaces opposite to each other. A roughness of each first side surface is different from a roughness of each second side surface.

公开(公告)号：US20240088279A1

公开(公告)日：2024-03-14

申请号：US18519099

申请日：2023-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Po-Wen Su ,  Chih-Tung Yeh

IPC: H01L29/778 ,  H01L21/311 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7781 ,  H01L21/31116 ,  H01L29/2003 ,  H01L29/66462

Abstract: A method for forming a semiconductor structure includes the steps of forming a stacked structure on a substrate, forming an insulating layer on the stacked structure, forming a passivation layer on the insulating layer, performing an etching process to form an opening through the passivation layer and the insulating layer to expose a portion of the stacked structure and an extending portion of the insulating layer, and forming a contact structure filling the opening and directly contacting the stacked structure, wherein the extending portion of the insulating layer is adjacent to a surface of the stacked structure directly contacting the contact structure.

公开(公告)号：US20240071988A1

公开(公告)日：2024-02-29

申请号：US17963227

申请日：2022-10-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju LI ,  Hsin-Jung LIU ,  Wei-Xin GAO ,  Jhih-Yuan CHEN ,  Ang CHAN ,  Chau-Chung HOU

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03452 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes: providing a substrate and a dielectric layer on the substrate; forming a hole in the dielectric layer; forming an initial barrier material layer and a conductive layer on an upper surface of the dielectric layer and in the hole; removing part of the initial barrier material layer and part of the conductive layer to form a barrier material layer and a via element in the hole respectively and expose the upper surface of the dielectric layer. An upper surface of the barrier material layer is higher than the upper surface of the dielectric layer.

公开(公告)号：US20240071758A1

公开(公告)日：2024-02-29

申请号：US17951119

申请日：2022-09-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  You-Jia Chang ,  Bo-Yu Chen ,  Yun-Chun Wang ,  Ruey-Chyr Lee ,  Wen-Jung Liao

IPC: H01L21/02 ,  H01L21/306 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L21/0254 ,  H01L21/30612 ,  H01L29/2003 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a gate electrode layer on the p-type semiconductor layer, and patterning the gate electrode layer to form a gate electrode. Preferably, the gate electrode includes an inclined sidewall.