公开(公告)号：US20080099230A1

公开(公告)日：2008-05-01

申请号：US11927144

申请日：2007-10-29

Applicant: Michimasa TAKAHASHI ,  Masakazu Aoyama

Inventor： Michimasa TAKAHASHI ,  Masakazu Aoyama

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/00

CPC classification number: H05K3/4691 ,  H05K1/0218 ,  H05K3/0035 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4664 ,  H05K2201/0187 ,  H05K2201/0715 ,  H05K2201/09127 ,  H05K2201/09509 ,  H05K2201/096 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A flex-rigid wiring board includes a flexible board including a flexible substrate and a conductor pattern formed over the flexible substrate, a non-flexible substrate disposed adjacent to the flexible board, an insulating layer including an inorganic material and covering the flexible board and the non-flexible substrate, the insulating layer exposing at least one portion of the flexible board, a conductor pattern formed on the insulating layer, and a plating layer connecting the conductor pattern of the flexible board and the conductor pattern on the insulating layer.

Abstract translation: 弹性刚性布线板包括柔性基板，该柔性基板包括柔性基板和形成在柔性基板上的导体图案，邻近柔性基板设置的非柔性基板，包括无机材料并覆盖柔性基板的绝缘层和 非柔性基板，绝缘层暴露柔性板的至少一部分，形成在绝缘层上的导体图案，以及将柔性基板的导体图案与导体图案连接在绝缘层上的镀层。

公开(公告)号：US07365568B1

公开(公告)日：2008-04-29

申请号：US11699114

申请日：2007-01-29

Applicant: Stephen M. Trimberger

Inventor： Stephen M. Trimberger

IPC: H03K19/177 ,  H01L25/00

CPC classification number: H03K19/1732 ,  H05K1/029 ,  H05K2201/09127 ,  H05K2201/10212 ,  H05K2201/10689

Abstract: A circuit board includes a large scale logic device and at least one outrigger device wherein signals having a transmission delay budget that exceed a threshold value are produced to the outrigger device for coupling to circuit devices of the circuit board that are external to the large scale logic device. One embodiment of the invention comprises a plurality of outrigger devices that communicate with the large scale logic device by way of parallel data buses, as well as multi-gigabit transceiver data lines. Logic within the outrigger devices is generally limited to signal routing and transmission logic. The large scale logic device further comprises logic to transmit and receive signals to and from the outrigger devices in a way that is transparent to internal logic of the large scale logic device.

Abstract translation: 电路板包括大规模逻辑器件和至少一个外伸支架装置，其中具有超过阈值的传输延迟预算的信号被产生到外伸支架装置，用于耦合到大规模逻辑外部的电路板的电路装置 设备。 本发明的一个实施例包括通过并行数据总线以及多吉比特收发器数据线与大规模逻辑设备通信的多个外伸支架设备。 外伸装置内的逻辑通常限于信号路由和传输逻辑。 大规模逻辑设备还包括以对大规模逻辑设备的内部逻辑透明的方式向外伸支架设备发送信号和从外伸支架设备接收信号的逻辑。

公开(公告)号：US20080051848A1

公开(公告)日：2008-02-28

申请号：US11928515

申请日：2007-10-30

Applicant: Robert Greenberg ,  Jerry Ok

Inventor： Robert Greenberg ,  Jerry Ok

IPC: A61N1/02

CPC classification number: A61N1/0543 ,  A61N1/36046 ,  A61N1/3752 ,  H01L23/057 ,  H01L23/10 ,  H01L23/4985 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/01079 ,  H01L2924/1461 ,  H05K1/0306 ,  H05K3/321 ,  H05K3/328 ,  H05K3/361 ,  H05K3/4015 ,  H05K3/423 ,  H05K3/4652 ,  H05K3/4691 ,  H05K2201/09127 ,  H05K2201/10287 ,  H05K2201/10295 ,  H05K2201/10977 ,  H05K2203/0733 ,  H05K2203/1446 ,  H01L2924/00

Abstract: The invention is directed to a method of bonding a hermetically sealed electronics package to an electrode or a flexible circuit and the resulting electronics package that is suitable for implantation in living tissue, such as for a retinal or cortical electrode array to enable restoration of sight to certain non-sighted individuals. The hermetically sealed electronics package is directly bonded to the flex circuit or electrode by electroplating a biocompatible material, such as platinum or gold, effectively forming a plated rivet-shaped connection, which bonds the flex circuit to the electronics package. The resulting electronic device is biocompatible and is suitable for long-term implantation in living tissue.

Abstract translation: 本发明涉及一种将气密密封的电子封装结合到电极或柔性电路的方法，以及所得的电子封装，其适于植入生物组织，例如用于视网膜或皮层电极阵列，以使视力恢复到 某些非目标人士。 电气密封的电子封装通过电镀生物相容性材料（例如铂或金）直接结合到柔性电路或电极上，有效地形成电镀铆钉形连接，其将柔性电路连接到电子封装。 所得到的电子装置是生物相容的并且适合长期植入生物体组织。

公开(公告)号：US07301230B2

公开(公告)日：2007-11-27

申请号：US11020226

申请日：2004-12-27

Applicant: Masateru Koide

Inventor： Masateru Koide

IPC: H01L23/12 ,  H05K1/18

CPC classification number: H01L23/50 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19106 ,  H05K1/183 ,  H05K3/0035 ,  H05K3/0044 ,  H05K3/381 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/09127 ,  H05K2201/09472 ,  H05K2201/10636 ,  H05K2203/0228 ,  Y02P70/611

Abstract: A laminating step includes a second step of laminating a second insulation layer on a conductive pattern last formed at a first step, roughening the surface of the laminated second insulation layer excluding a desired area, and forming a conductive layer on at least the desired area of the surface of the second insulation layer, and a processing step includes a removing step of removing an upper part of the area higher than the second insulation layer on the substrate obtained at the laminating step, and an exposing step of exposing a part of the area of a conductive pattern adjacent to the lower side of the second insulation layer.

Abstract translation: 层压步骤包括第二步骤，将第二绝缘层层压在最后形成的第一步骤的导电图案上，使层压的第二绝缘层的表面粗糙化，除去期望的区域，并且在至少所需的区域上形成导电层 第二绝缘层的表面和加工步骤包括去除在层压步骤获得的基板上高于第二绝缘层的区域的上部的去除步骤，以及暴露步骤， 的导电图案与第二绝缘层的下侧相邻。

公开(公告)号：US20070207569A1

公开(公告)日：2007-09-06

申请号：US11517859

申请日：2006-09-07

Applicant: Robert J. Greenberg ,  Jerry Ok

Inventor： Robert J. Greenberg ,  Jerry Ok

IPC: H01L21/00

CPC classification number: A61N1/0543 ,  A61N1/36046 ,  A61N1/3752 ,  H01L23/057 ,  H01L23/10 ,  H01L23/4985 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/01079 ,  H01L2924/1461 ,  H05K1/0306 ,  H05K3/321 ,  H05K3/328 ,  H05K3/361 ,  H05K3/4015 ,  H05K3/423 ,  H05K3/4652 ,  H05K3/4691 ,  H05K2201/09127 ,  H05K2201/10287 ,  H05K2201/10295 ,  H05K2201/10977 ,  H05K2203/0733 ,  H05K2203/1446 ,  H01L2924/00

Abstract: The invention is directed to a method of bonding a hermetically sealed electronics package to an electrode or a flexible circuit and the resulting electronics package that is suitable for implantation in living tissue, such as for a retinal or cortical electrode array to enable restoration of sight to certain non-sighted individuals. The hermetically sealed electronics package is directly bonded to the flex circuit or electrode by electroplating a biocompatible material, such as platinum or gold, effectively forming a plated rivet-shaped connection, which bonds the flex circuit to the electronics package. The resulting electronic device is biocompatible and is suitable for long-term implantation in living tissue.

Abstract translation: 本发明涉及一种将气密密封的电子封装结合到电极或柔性电路的方法，以及所得的电子封装，其适于植入生物组织，例如用于视网膜或皮层电极阵列，以使视力恢复到 某些非目标人士。 密封电子封装通过电镀生物相容性材料（例如铂或金）直接结合到柔性电路或电极上，有效地形成电镀铆钉形连接，其将柔性电路连接到电子封装。 所得到的电子装置是生物相容的并且适合长期植入生物体组织。

公开(公告)号：US07264487B2

公开(公告)日：2007-09-04

申请号：US10886113

申请日：2004-07-06

Applicant: Fang-Jwu Liao

Inventor： Fang-Jwu Liao

IPC: H01R13/44

CPC classification number: H01R43/205 ,  H01R12/7076 ,  H05K3/303 ,  H05K3/3494 ,  H05K2201/09127 ,  H05K2201/10189 ,  H05K2203/081 ,  H05K2203/082 ,  Y02P70/613 ,  Y10S439/94

Abstract: An electrical connector assembly (1) includes an LGA connector (2) having a metal clip (25) and a pick up cap (3). The pick up cap has a planar body (30) forming a plane top surface (300). Several holes (302, 303, 309) are defined in the planar body. When the pick up cap is engagingly mounted onto a top portion of the connector, the holes are in communication with a window (258) of the clip. A vacuum suction device can engage the top surface of the pick up cap to move the connector assembly to a desired location on a PCB. When curing adhesive film at high temperature, heated air can flow through the holes to a bottom portion of the connector. Reliable electrical connection between the contacts of the connector and the metal contact pads of the PCB is subsequently produced in a wave solder machine or drag soldering equipment.

Abstract translation: 电连接器组件（1）包括具有金属夹（25）和拾取盖（3）的LGA连接器（2）。 拾取盖具有形成平面顶表面（300）的平面体（30）。 在平面体中限定了几个孔（302,303,309）。 当拾取盖被接合地安装到连接器的顶部时，孔与夹子的窗口（258）连通。 真空抽吸装置可以接合拾取盖的顶表面，以将连接器组件移动到PCB上的期望位置。 当在高温下固化粘合剂膜时，加热的空气可以通过孔流到连接器的底部。 连接器的触点和PCB的金属接触垫之间的可靠电连接随后在波峰焊机或拖曳焊接设备中产生。

公开(公告)号：US07187202B1

公开(公告)日：2007-03-06

申请号：US10956210

申请日：2004-09-30

Applicant: Stephen M. Trimberger

Inventor： Stephen M. Trimberger

IPC: H03K19/173 ,  H01L25/00

CPC classification number: H03K19/1732 ,  H05K1/029 ,  H05K2201/09127 ,  H05K2201/10212 ,  H05K2201/10689

Abstract: A circuit board includes a large scale logic device and at least one outrigger device wherein signals having a transmission delay budget that exceed a threshold value are produced to the outrigger device for coupling to circuit devices of the circuit board that are external to the large scale logic device. One embodiment of the invention comprises a plurality of outrigger devices that communicate with the large scale logic device by way of parallel data buses, as well as multi-gigabit transceiver data lines. Logic within the outrigger devices is generally limited to signal routing and transmission logic. The large scale logic device further comprises logic to transmit and receive signals to and from the outrigger devices in a way that is transparent to internal logic of the large scale logic device.

Abstract translation: 电路板包括大规模逻辑器件和至少一个外伸支架装置，其中具有超过阈值的传输延迟预算的信号被产生到外伸支架装置，用于耦合到大规模逻辑外部的电路板的电路装置 设备。 本发明的一个实施例包括通过并行数据总线以及多吉比特收发器数据线与大规模逻辑设备通信的多个外伸支架设备。 外伸装置内的逻辑通常限于信号路由和传输逻辑。 大规模逻辑设备还包括以对大规模逻辑设备的内部逻辑透明的方式向外伸支架设备发送信号和从外伸支架设备接收信号的逻辑。

公开(公告)号：US20050099784A1

公开(公告)日：2005-05-12

申请号：US11021169

申请日：2004-12-21

Applicant: Robert Wallace

Inventor： Robert Wallace

IPC: G11C5/00 ,  H01L21/56 ,  H01L23/24 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/28 ,  H05K7/06

CPC classification number: G11C5/06 ,  G11C5/04 ,  G11C16/04 ,  G11C29/1201 ,  G11C29/48 ,  H01L21/565 ,  H01L23/24 ,  H01L23/3107 ,  H01L23/5388 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0655 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0268 ,  H05K1/117 ,  H05K3/0052 ,  H05K3/284 ,  H05K2201/09127 ,  H05K2201/10689 ,  H05K2201/2018

Abstract: A small package is provided for a flash EEPROM memory. The small package uses terminals which are part of a bottom conductive layer of a circuit board. In this manner, the final package can be quite thin. The circuit board can be connected to the integrated circuits and passive devices and can be encapsulated in plastic or glued to a plastic cover. In this manner, a thin and relatively inexpensive package can be formed. Additionally, the circuit board can have testing connections which can be removed before forming the final package.

公开(公告)号：US06867485B2

公开(公告)日：2005-03-15

申请号：US09866022

申请日：2001-05-24

Applicant: Robert F. Wallace

Inventor： Robert F. Wallace

IPC: G11C5/00 ,  H01L21/56 ,  H01L23/24 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/28 ,  H01L23/02

CPC classification number: G11C5/06 ,  G11C5/04 ,  G11C16/04 ,  G11C29/1201 ,  G11C29/48 ,  H01L21/565 ,  H01L23/24 ,  H01L23/3107 ,  H01L23/5388 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0655 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0268 ,  H05K1/117 ,  H05K3/0052 ,  H05K3/284 ,  H05K2201/09127 ,  H05K2201/10689 ,  H05K2201/2018

Abstract: A small package is provided for a flash EEPROM memory. The small package uses terminals which are part of a bottom conductive layer of a circuit board. In this manner, the final package can be quite thin. The circuit board can be connected to the integrated circuits and passive devices and can be encapsulated in plastic or glued to a plastic cover. In this manner, a thin and relatively inexpensive package can be formed. Additionally, the circuit board can have testing connections which can be removed before forming the final package.

Abstract translation: 提供了一个用于闪存EEPROM存储器的小封装。 小封装使用作为电路板的底部导电层的一部分的端子。 以这种方式，最终的包装可以相当薄。 电路板可以连接到集成电路和无源器件，并且可以封装在塑料中或胶合到塑料盖上。 以这种方式，可以形成薄且相对便宜的包装。 此外，电路板可以具有可以在形成最终封装之前被去除的测试连接。

公开(公告)号：US20050014419A1

公开(公告)日：2005-01-20

申请号：US10918081

申请日：2004-08-12

Applicant: Tom Pearson ,  George Arrigotti ,  Christopher Combs ,  Raiyomand Aspandiar

Inventor： Tom Pearson ,  George Arrigotti ,  Christopher Combs ,  Raiyomand Aspandiar

IPC: H05K1/14 ,  H05K3/34 ,  H01R9/22

CPC classification number: H05K3/3405 ,  H05K1/142 ,  H05K2201/09127 ,  H05K2201/10204 ,  H05K2201/10446 ,  H05K2201/209 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/5313 ,  Y10T29/53252

Abstract: A mechanism and method are provided for assembling a printed circuit board having a first surface, a second surface and an edge. The printed circuit board may include at least one female member to receive a corresponding male member. The mechanism may include an extension board having an edge to couple to the edge of the printed circuit board. The extension board may include a male member to extend from the edge of the extension board and to couple to the at least one male member so as to couple the extension board to the printed circuit board.

Abstract translation: 提供了用于组装具有第一表面，第二表面和边缘的印刷电路板的机构和方法。 印刷电路板可以包括至少一个阴构件以接收相应的阳构件。 该机构可以包括具有连接到印刷电路板的边缘的边缘的延伸板。 延伸板可以包括从延伸板的边缘延伸并连接到至少一个阳构件的阳构件，以便将延伸板耦合到印刷电路板。