公开(公告)号：US09514811B2

公开(公告)日：2016-12-06

申请号：US15052627

申请日：2016-02-24

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Christophe J. Chevallier ,  Chang Hua Siau

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/21

CPC classification number: G11C13/0033 ,  G11C11/21 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069

Abstract: Systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and an access signal generator. The access signal generator can be configured to access a resistive memory element in the cross-point array.

Abstract translation: 描述了用于产生访问信号的系统，集成电路和方法以促进存储器元件的缩放阵列中的存储器操作。 在至少一些实施例中，非易失性存储器件可以包括具有电阻存储器元件和存取信号发生器的交叉点阵列。 访问信号发生器可被配置为访问交叉点阵列中的电阻性存储器元件。

公开(公告)号：US20160172025A1

公开(公告)日：2016-06-16

申请号：US15052627

申请日：2016-02-24

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Christophe J. Chevallier ,  Chang Hua Siau

IPC: G11C13/00

CPC classification number: G11C13/0033 ,  G11C11/21 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069

Abstract: Systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and an access signal generator. The access signal generator can be configured to access a resistive memory element in the cross-point array.

Abstract translation: 描述了用于产生访问信号的系统，集成电路和方法以促进存储器元件的缩放阵列中的存储器操作。 在至少一些实施例中，非易失性存储器件可以包括具有电阻存储器元件和存取信号发生器的交叉点阵列。 访问信号发生器可被配置为访问交叉点阵列中的电阻性存储器元件。

公开(公告)号：US09299427B2

公开(公告)日：2016-03-29

申请号：US14624891

申请日：2015-02-18

Applicant: Unity Semiconductor Corporation

Inventor： Christophe J. Chevallier ,  Chang Hua Siau

IPC: G11C13/00 ,  G11C11/21

CPC classification number: G11C13/0033 ,  G11C11/21 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a FEOL substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator. The access signal generator can be configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. The modified magnitude can be a function of the position of the resistive memory element in the cross-point array.

公开(公告)号：US20150262664A1

公开(公告)日：2015-09-17

申请号：US14727190

申请日：2015-06-01

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Robert Norman

IPC: G11C13/00

CPC classification number: G11C13/0035 ,  G11C5/005 ,  G11C5/02 ,  G11C11/16 ,  G11C13/0002 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/77

Abstract: Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.

Abstract translation: 公开了用于恢复存储器中的数据的电路和方法。 存储器可以包括非易失性两端交叉点阵列的至少一层，其包括将数据存储为多个电导率分布并且在没有电力的情况下保存存储的数据的多个两端存储器元件。 在一段时间内，指示存储的数据的逻辑值可能漂移，使得如果逻辑值不被恢复，则所存储的数据可能被破坏。 每个存储器的至少一部分可以具有与存储器电耦合的电路重写或恢复的数据。 可以使用其他电路来确定用于对存储器执行恢复操作的调度，并且恢复操作可以由内部或外部信号或事件来触发。 电路可以定位在逻辑层中，并且存储器可以在逻辑层上制造。

公开(公告)号：US20150222251A1

公开(公告)日：2015-08-06

申请号：US14688060

申请日：2015-04-16

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Chang Hua Siau

IPC: H03K3/356 ,  G11C8/08 ,  G11C13/00

CPC classification number: G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0007 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/77 ,  H03K3/356104 ,  H03K19/018521

Abstract: Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example.

Abstract translation: 公开了用于产生用于对非易失性可重写存储器阵列执行数据操作的电压电平的电路。 在一些实施例中，集成电路包括衬底和形成在衬底上的基底层，以包括被配置为在第一电压范围内操作的有源器件。 此外，集成电路可以包括形成在基极层上方的交叉点存储器阵列，并且包括可重写的两端存储器单元，其被配置为例如在大于第一电压范围的第二电压范围内操作 。 交叉点存储器阵列中的导电阵列线与基极层中的有源器件电耦合。 集成电路还可以包括X线解码器和Y线解码器，其中包括在第一电压范围内工作的器件。 有源器件可以包括其他有源电路，例如用于从存储器单元读取数据的感测放大器。

公开(公告)号：US09053756B2

公开(公告)日：2015-06-09

申请号：US14068754

申请日：2013-10-31

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Christophe Chevallier ,  Robert Norman

IPC: G11C11/16 ,  G11C5/00 ,  G11C5/02

CPC classification number: G11C13/0035 ,  G11C5/005 ,  G11C5/02 ,  G11C11/16 ,  G11C13/0002 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/77

Abstract: Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.

Abstract translation: 公开了用于恢复存储器中的数据的电路和方法。 存储器可以包括非易失性两端交叉点阵列的至少一层，其包括将数据存储为多个电导率分布并且在没有电力的情况下保存存储的数据的多个两端存储器元件。 在一段时间内，指示存储的数据的逻辑值可能漂移，使得如果逻辑值不被恢复，则所存储的数据可能被破坏。 每个存储器的至少一部分可以具有与存储器电耦合的电路重写或恢复的数据。 可以使用其他电路来确定用于对存储器执行恢复操作的调度，并且恢复操作可以由内部或外部信号或事件来触发。 电路可以定位在逻辑层中，并且存储器可以在逻辑层上制造。

公开(公告)号：US20150138874A1

公开(公告)日：2015-05-21

申请号：US14568025

申请日：2014-12-11

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Chang Hua Siau

IPC: G11C13/00

CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G11C5/06 ,  G11C8/08 ,  G11C11/419 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0021 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/72

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.

Abstract translation: 本发明的实施例大体上涉及半导体和存储器技术，更具体地涉及系统，集成电路和保持存储器元件的状态的方法，该数据与使用其他存储器元件的可变存取信号幅度的数据操作相关联，例如在第三 三维存储技术。 在一些实施例中，存储器件可以包括具有电阻存储元件的交叉点阵列。 访问信号发生器可以修改信号的幅度以产生用于信号访问与字线和位线的子集相关联的电阻性存储器元件的修改幅度。 跟踪信号发生器被配置为跟踪信号的经修改的幅度，并将跟踪信号施加到与其他子位位线相关联的其他电阻性存储元件，跟踪信号具有与信号的修改幅度不同的量级 。

公开(公告)号：US20150014760A1

公开(公告)日：2015-01-15

申请号：US14314622

申请日：2014-06-25

Applicant: Unity Semiconductor Corporation

Inventor： Bruce Lynn Bateman

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/3418 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/66833 ,  H01L29/7926

Abstract: In an example, a device comprises a vertical stack of memory cells. Each memory cell of the vertical stack may include more than one memory element. A first vertical gate line may be coupled to a first one of the memory elements in each memory cell, and a second vertical gate line may be coupled to a second one of the memory elements in each memory cell. The first vertical gate line may be electrically isolated from the second vertical gate line.

Abstract translation: 在一个示例中，设备包括垂直堆叠的存储器单元。 垂直堆栈的每个存储单元可以包括多于一个存储元件。 第一垂直栅极线可以耦合到每个存储器单元中的存储器元件中的第一个，并且第二垂直栅极线可以耦合到每个存储器单元中的第二个存储器元件。 第一垂直栅极线可以与第二垂直栅极线电隔离。

公开(公告)号：US08929126B2

公开(公告)日：2015-01-06

申请号：US14024946

申请日：2013-09-12

Applicant: Unity Semiconductor Corporation

Inventor： Chang Hua Siau

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/419 ,  G11C8/08 ,  G11C5/06

CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G11C5/06 ,  G11C8/08 ,  G11C11/419 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0021 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/72

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.

Abstract translation: 本发明的实施例大体上涉及半导体和存储器技术，更具体地涉及系统，集成电路和保持存储器元件的状态的方法，该数据与使用其他存储器元件的可变存取信号幅度的数据操作相关联，例如在第三 三维存储技术。 在一些实施例中，存储器件可以包括具有电阻存储元件的交叉点阵列。 访问信号发生器可以修改信号的幅度以产生用于信号访问与字线和位线的子集相关联的电阻性存储器元件的修改幅度。 跟踪信号发生器被配置为跟踪信号的经修改的幅度，并将跟踪信号施加到与其他子位位线相关联的其他电阻性存储元件，跟踪信号具有与信号的修改幅度不同的量级 。

公开(公告)号：US08901962B2

公开(公告)日：2014-12-02

申请号：US14024891

申请日：2013-09-12

Applicant: Unity Semiconductor Corporation

Inventor： Robert Norman

IPC: H01L25/00 ,  H03K19/177

CPC classification number: H03K19/1776 ,  H03K19/17748 ,  H03K19/1778 ,  H03K19/17796

Abstract: A Programmable Logic Device (PLD) structure using third dimensional memory is disclosed. The PLD structure includes a switch configured to couple a polarity of a signal (e.g., an input signal applied to an input) to a routing line and a non-volatile register configured to control the switch. The non-volatile register may include a non-volatile memory element, such as a third dimension memory element. The non-volatile memory element may be a two-terminal memory element that retains stored data in the absence of power and stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage across the two terminals. Logic and other active circuitry can be positioned in a substrate and the non-volatile memory element can be positioned on top of the substrate.

Abstract translation: 公开了一种使用第三维存储器的可编程逻辑器件（PLD）结构。 PLD结构包括被配置为将信号的极性（例如，施加到输入的输入信号）耦合到路由线路的开关和被配置为控制开关的非易失性寄存器。 非易失性寄存器可以包括诸如第三维存储元件的非易失性存储元件。 非易失性存储器元件可以是在没有电力的情况下保存存储的数据并将数据存储为可以通过在两个端子上施加读取电压而被非破坏性地感测的多个电导率分布的两端存储元件。 可以通过在两个端子上施加写入电压将新数据写入到两端存储元件。 逻辑和其它有源电路可以被定位在衬底中，并且非易失性存储元件可以被定位在衬底的顶部上。