公开(公告)号：US6071597A

公开(公告)日：2000-06-06

申请号：US919883

申请日：1997-08-28

Applicant: Rui Yang ,  Thach G. Truong ,  Justine A. Mooney ,  Moses M. David

Inventor： Rui Yang ,  Thach G. Truong ,  Justine A. Mooney ,  Moses M. David

IPC: H01L21/60 ,  H01L23/498 ,  H01L23/538 ,  H05K1/00 ,  H05K3/28 ,  H05K3/38 ,  B32B9/00

CPC classification number: H01L23/4985 ,  H01L23/5387 ,  H05K3/28 ,  H05K3/388 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0393 ,  H05K2201/0179 ,  H05K2201/0323 ,  Y10T428/24917 ,  Y10T428/30

Abstract: A flexible circuit carrier including at least one layer of polymer dielectric material, at least one layer of conductive material thereover, each layer having two major surfaces, at least one of said layers having at least one aperture therein, wherein at least one layer has a material coated on at least a portion thereof having a Young's Modulus of from about 100 to about 200 GPa, a dielectric constant (between 45 MHz and 20 GHz) of from about 8 to about 12, and a Vickers hardness of from about 2000 to about 9000 kg/mm.sup.2.

Abstract translation: 一种柔性电路载体，其包括至少一层聚合物电介质材料，至少一层导电材料，其中每层具有两个主表面，至少一层所述层中至少有一个孔，其中至少一层具有 涂覆在其至少一部分上的材料具有约100至约200GPa的杨氏模量，约8至约12的介电常数（在45MHz和20GHz之间），维氏硬度为约2000至约 9000 kg / mm2。

公开(公告)号：US6005197A

公开(公告)日：1999-12-21

申请号：US918216

申请日：1997-08-25

Applicant: Ratnaji Roa Kola ,  Louis Thomas Manzione ,  Roderick Kent Watts

Inventor： Ratnaji Roa Kola ,  Louis Thomas Manzione ,  Roderick Kent Watts

IPC: B32B9/00 ,  H01L23/12 ,  H05K1/16 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2203/0315 ,  H05K3/429 ,  Y10T29/435 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: The specification describes of multilevel printed circuit boards and a process for their manufacture in which capacitors and other passive components are buried between levels of the multilevel board. The capacitor in the multilevel structure is designed so that access is conveniently provided to connect from the parallel plate electrodes of the interlevel capacitor to the board surface or to another board level using plated through hole interconnects.

Abstract translation: 本说明书描述了多层印刷电路板及其制造方法，其中电容器和其它无源部件被埋在多层板的层级之间。 多层结构中的电容器被设计成使得通过电镀通孔互连方便地提供接入以从层间电容器的平行板电极到板表面或另一个板级连接。

公开(公告)号：US5912044A

公开(公告)日：1999-06-15

申请号：US782205

申请日：1997-01-10

Applicant: Mukta Shaji Farooq ,  Ajay P. Giri ,  Rajesh Shankerial Patel

Inventor： Mukta Shaji Farooq ,  Ajay P. Giri ,  Rajesh Shankerial Patel

IPC: H01L21/02 ,  H05K1/03 ,  H05K1/16 ,  H05K3/00 ,  H05K3/46 ,  B05D5/12

CPC classification number: H01L28/40 ,  H01L28/55 ,  H05K1/162 ,  H05K1/0306 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K3/0029 ,  H05K3/4605 ,  Y10T29/435

Abstract: Thin film capacitors are formed by a multi-level dry processing method that includes simultaneous ablation of via openings through both the dielectric and the metal electrode layers of a capacitor. Preferably, the dielectric films are formed of barium strontium titanate and the metal electrode layers are formed of platinum. The present invention overcomes the problems associated with the use of strong etchants to sequentially form separate via openings through the electrode and dielectric layers, prevents the potential for delamination of the respective layers during wet etching and the possible undesirable effects of etching solutions on substrate materials.

Abstract translation: 薄膜电容器通过多级干法处理方法形成，其包括通过电容器的电介质和金属电极层的同时烧蚀通孔。 优选地，电介质膜由钛酸钡锶形成，并且金属电极层由铂形成。 本发明克服了与使用强蚀刻剂顺序地通过电极和电介质层形成单独的通路孔相关的问题，防止在湿蚀刻期间各层分层的可能性以及蚀刻溶液对衬底材料的可能不期望的影响。

公开(公告)号：US5874770A

公开(公告)日：1999-02-23

申请号：US731172

申请日：1996-10-10

Applicant: Richard Joseph Saia ,  Kevin Matthew Durocher ,  Herbert Stanley Cole

Inventor： Richard Joseph Saia ,  Kevin Matthew Durocher ,  Herbert Stanley Cole

IPC: H05K3/46 ,  H01L21/48 ,  H01L21/822 ,  H01L21/98 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L27/04 ,  H05K1/16 ,  H05K3/38 ,  H05K3/40 ,  H05K3/42 ,  H01L23/053 ,  H01L23/02 ,  H01L23/48

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/5385 ,  H01L24/18 ,  H01L24/82 ,  H01L25/16 ,  H01L25/50 ,  H05K1/162 ,  H05K1/167 ,  H01L2224/18 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0315 ,  H05K2203/0361 ,  H05K3/388 ,  H05K3/4076 ,  H05K3/426 ,  H05K3/4644 ,  Y10T29/49165

Abstract: A method for fabricating a flexible interconnect film includes applying a resistor layer over one or both surfaces of a dielectric film; applying a metallization layer over the resistor layer with the resistor layer including a material facilitating adhesion of the dielectric film and the metallization layer; applying a capacitor dielectric layer over the metallization layer; and applying a capacitor electrode layer over the capacitor dielectric layer. The capacitor electrode layer is patterned to form a first capacitor electrode; the capacitor dielectric layer is patterned; the metallization layer is patterned to form a resistor; and the metallization layer and the resistor layer are patterned to form an inductor and a second capacitor electrode. In one embodiment, the dielectric film includes a polyimide, the resistor layer includes tantalum nitride, and the capacitor dielectric layer includes amorphous hydrogenated carbon or tantalum oxide. If the resistor and metallization layers are applied over both surfaces of the dielectric film, passive components can be fabricated on both surfaces of the dielectric film. The dielectric film can have vias therein with the resistor and metallization layers extending through the vias. A circuit chip can be attached and coupled to the passive components by metallization patterned through vias in an additional dielectric layer.

Abstract translation: 制造柔性互连膜的方法包括在电介质膜的一个或两个表面上施加电阻层; 在所述电阻层上施加金属化层，所述电阻层包括促进所述电介质膜和所述金属化层的粘附的材料; 在所述金属化层上施加电容器电介质层; 以及在电容器电介质层上施加电容器电极层。 将电容器电极层图案化以形成第一电容器电极; 对电容器电介质层进行图案化; 图案化金属化层以形成电阻器; 并且金属化层和电阻层被图案化以形成电感器和第二电容器电极。 在一个实施例中，电介质膜包括聚酰亚胺，电阻层包括氮化钽，电容器介电层包括无定形氢化碳或氧化钽。 如果将电阻和金属化层施加在电介质膜的两个表面上，则可以在电介质膜的两个表面上制造无源元件。 电介质膜可以具有通孔，其中电阻器和金属化层延伸穿过通孔。 电路芯片可以通过在附加电介质层中通过通孔图案化的金属化而附接并耦合到无源部件。

公开(公告)号：US5796572A

公开(公告)日：1998-08-18

申请号：US616723

申请日：1996-03-15

Applicant: Wakahiro Kawai

Inventor： Wakahiro Kawai

IPC: H01G4/08 ,  H01G4/33 ,  H01L27/01 ,  H05K1/14 ,  H05K1/16 ,  H05K3/10 ,  H05K3/24 ,  H05K3/38 ,  H01G4/10 ,  H01G4/06

CPC classification number: H01G4/08 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0338 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09763 ,  H05K3/102 ,  H05K3/245 ,  H05K3/38 ,  H05K3/383 ,  Y10T29/43 ,  Y10T29/435

Abstract: A high-capacitance thin film capacitc is compact and has a low profile. A dielectric layer 3 is formed between opposed electrodes 1 and 2. Between the electrodes and the dielectric layer are two layers of conductive particles, 4 and 5.

Abstract translation: 高电容薄膜电容紧凑，外形小巧。 介电层3形成在相对的电极1和2之间。电极和电介质层之间是两层导电颗粒4和5。

公开(公告)号：US5745333A

公开(公告)日：1998-04-28

申请号：US342507

申请日：1994-11-21

Applicant: Jerome Albert Frankeny ,  Richard Francis Frankeny ,  Terry Frederick Hayden ,  Ronald Lann Imken ,  Janet Louise Rice

Inventor： Jerome Albert Frankeny ,  Richard Francis Frankeny ,  Terry Frederick Hayden ,  Ronald Lann Imken ,  Janet Louise Rice

IPC: H05K1/16 ,  H05K3/46 ,  H01G4/06

CPC classification number: H05K3/462 ,  H05K1/162 ,  H05K3/4641 ,  H01L2224/81385 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2203/0307 ,  H05K3/4623 ,  Y10T29/435 ,  Y10T29/49165 ,  Y10T29/49169

Abstract: Method and apparatus for fabricating fine pitch pattern multilayer printed circuit boards involving laminar stackable board layers providing power distribution, signal distribution and capacitive decoupling. In one respect, the invention relates to the fabrication of board layers by beginning with a metallic core, patterning the core, selectively enclosing the core in a dielectric, selectively depositing metal to form vias, plugs and signal lines, and forming dendrites with joining metallurgy on the vias and plugs to provide stackable connection from above or below the plane of the board layer. In another aspect, the invention is directed to the use of a sol-gel process to form a thin high dielectric constant crystalline film onto a metallic sheet followed with a deposition of a metallic layer onto the high dielectric constant film. The film serves as the dielectric of a capacitor layer which is thereafter in succession patterned, covered by a dielectric, and has selectively deposited a metallic layer for interconnecting the capacitor and forming vias. The ends of the vias are thereafter subject to dendritic growth and joining metallurgy to provide stackable interconnection capability. A multilayer composite laminar stackable circuit board structure is created using, as appropriate, layers having metallic cores and layers having capacitively configured cores. The multilayer laminar stackable circuit board provides direct vertical connection between surface mounted electronic components and the power, signal and capacitive decoupling layers of the composite board through the dendrites and joining metallurgy of the via and plug formations.

公开(公告)号：US5111003A

公开(公告)日：1992-05-05

申请号：US665938

申请日：1991-03-06

Applicant: Kohji Kimbara

Inventor： Kohji Kimbara

IPC: H01F17/00 ,  H05K1/03 ,  H05K3/38 ,  H05K3/46

CPC classification number: H01F17/0013 ,  H05K3/4605 ,  H05K1/0306 ,  H05K1/0346 ,  H05K2201/0154 ,  H05K2201/0179 ,  H05K2203/1581 ,  H05K3/388 ,  H05K3/467 ,  Y10T428/12556 ,  Y10T428/12583 ,  Y10T428/12875 ,  Y10T428/12889 ,  Y10T428/24851 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/31612 ,  Y10T428/31623 ,  Y10T428/31681 ,  Y10T428/31721 ,  Y10T428/31765

Abstract: A multilayer wiring substrate which includes a glass ceramic section, a wiring layer section having a plurality of wiring layers electrically insulated from each other by a polyimide material, and an intermediate layer made of an inorganic material and arranged between the ceramic section and the wiring layer section. 8

公开(公告)号：US4713284A

公开(公告)日：1987-12-15

申请号：US943695

申请日：1986-12-19

Applicant: Hiroshi Hasegawa ,  Mitsuhiro Inoue

Inventor： Hiroshi Hasegawa ,  Mitsuhiro Inoue

IPC: B32B15/08 ,  H05K1/03 ,  H05K3/38 ,  B32B7/00

CPC classification number: B32B15/08 ,  H05K1/036 ,  H05K3/38 ,  H05K1/0306 ,  H05K2201/0179 ,  H05K2201/0355 ,  H05K2203/066 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T442/3423

Abstract: Ceramic coated laminates for printed circuit boards produced by flame spraying a ceramic powder on a metal plate such as copper foil or a woven fabric prepreg, laminating one or two ceramic coated metal plates and woven fabric prepregs so as to place the ceramic layer between the metal plate and the prepreg, hot-pressing the laminated members, and if necessary peeling off the metal plate(s), are excellent in thermal conductivity and heat resistance.

Abstract translation: 用于印刷电路板的陶瓷涂层层压板，通过将陶瓷粉末火焰喷涂在诸如铜箔或机织织物预浸料的金属板上，层压一个或两个陶瓷涂覆的金属板和机织织物预浸料，以将陶瓷层放置在金属 板和预浸料坯，热压层压部件，如果需要，则剥离金属板，导热性和耐热性优异。

公开(公告)号：US4302737A

公开(公告)日：1981-11-24

申请号：US105946

申请日：1979-12-20

Applicant: Helmold Kausche ,  Heinz Hebbeker

Inventor： Helmold Kausche ,  Heinz Hebbeker

IPC: H01C17/24 ,  H01C13/02 ,  H01C17/242 ,  H01G4/255 ,  H01L27/01 ,  H03H1/02 ,  H03H7/06 ,  H05K1/00 ,  H05K1/16 ,  H05K3/02 ,  H03H3/00 ,  H03H7/01

CPC classification number: H05K1/162 ,  H01C13/02 ,  H01C17/242 ,  H01L27/01 ,  H05K1/0393 ,  H05K1/167 ,  H05K2201/0166 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09763 ,  H05K2203/171 ,  H05K3/027 ,  Y10T29/49082 ,  Y10T29/49099

Abstract: An RC network is disclosed in which two electrically conducting regions and a dielectric lying between these regions form a capacitor. At least one of the electrically conducting regions consists of resistance material and is designed in the shape of a meandering path. This network can be balanced while still guaranteeing a uniform region distribution of the resistance and the capacitance, by means of a laser beam. Upon a carrier of heat-resistant material, a resistance layer, a dielectric of glow discharge polymer, and an opposite electrode capable of regeneration, are applied. The dielectric completely covers the resistance layer with the exception of contact pads.

Abstract translation: 公开了一种RC网络，其中两个导电区域和位于这些区域之间的电介质形成电容器。 至少一个导电区域由电阻材料构成，并且被设计成曲折路径的形状。 该网络可以平衡，同时通过激光束保证电阻和电容的均匀区域分布。 在耐热材料的载体上施加电阻层，辉光放电聚合物的电介质和能够再生的相对电极。 电介质完全覆盖电阻层，接触垫除外。

公开(公告)号：US3895135A

公开(公告)日：1975-07-15

申请号：US35621373

申请日：1973-05-01

Applicant: UNION CARBIDE CORP

Inventor： HOFER PETER H

IPC: C23C14/12 ,  H01L49/02 ,  H05K3/06 ,  H05K3/28 ,  H05K3/46 ,  B44D1/52

CPC classification number: H05K3/284 ,  H01L49/02 ,  H05K2201/0179

Abstract: A masking process, during the vapor deposition coating of a partially masked substrate with a condensible vaporous precursor of a coating material, which comprises causing the vaporous precursor to flow through a constricted flow path at the masked/unmasked interface during the coating process so as to provide a relatively thin coating at the end of the flow path which can be used as a tear line for removing the coating masking means along such interface.

Abstract translation: 在具有可涂覆材料的可冷凝蒸气前体的部分掩蔽的基底的气相沉积涂覆期间的掩模工艺，其包括在涂覆过程期间使蒸气前体在掩蔽/未掩蔽的界面处流过狭窄的流动路径，以便 在流动路径的末端提供相对薄的涂层，其可以用作沿着这种界面去除涂层掩蔽装置的撕裂线。