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公开(公告)号：US12282776B2
公开(公告)日：2025-04-22
申请号：US17708344
申请日：2022-03-30
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Anthony Jarvis , Thomas Clouqueur
IPC: G06F9/38
Abstract: Hybrid parallelized tagged geometric (TAGE) branch prediction, including: selecting, based on a branch instruction, a first plurality of counts from at least one TAGE table; selecting, based on the branch instruction, a second plurality of counts from at least one non-TAGE branch prediction table; generating, based on the first plurality of counts and a second plurality of counts; and wherein selecting the first plurality of counts and selecting the second plurality of counts are performed during a same branch prediction pipeline stage.
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公开(公告)号：US20250126096A1
公开(公告)日：2025-04-17
申请号：US18380621
申请日：2023-10-16
Applicant: Advanced Micro Devices, Inc.
Inventor： Shrey AJMERA , Enrico SCHIATTARELLA
IPC: H04L41/069 , H04L9/40
Abstract: Rather than collecting flow logs at a central location, and then processing these flow logs to create general purpose or specialized data stores, the embodiments herein rely on the network appliances to create the flow logs and metadata that indexes these flow logs. The flow logs and the metadata can then be collected at the central location (e.g., a central analyzer) and merged with flow logs and metadata generated by other network appliances to yield a data store that can be used to analyze the flow logs in computing environment (e.g., a data center).
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公开(公告)号：US12278638B2
公开(公告)日：2025-04-15
申请号：US18525071
申请日：2023-11-30
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Kaushik Mazumdar , Ashish Jain , Joyce Cheuk Wai Wong , Mikhail Rodionov
IPC: H03L7/08 , G01R19/165
Abstract: An integrated circuit includes a power supply monitor, a clock generator, and a divider. The power supply monitor is operable to provide a trigger signal in response to a power supply voltage dropping below a threshold voltage. The clock generator is operable to provide a first clock signal having a frequency dependent on a value of a frequency control word, and to change the frequency of the first clock signal over time using a native slope in response to a change in the frequency control word. The divider is responsive to an assertion of the trigger signal to divide a frequency of the first clock signal by a divide value to provide a second clock signal.
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公开(公告)号：US20250117523A1
公开(公告)日：2025-04-10
申请号：US18911080
申请日：2024-10-09
Applicant: ATI Technologies ULC , Advanced Micro Devices, Inc.
Inventor： Valeri Kirischian , Steven Leonard Roberts , Ruchir Badola
IPC: G06F21/70
Abstract: A method can include overriding settings of an integrated circuit device by reading one or more settings from a setting record that correspond to a part number of the integrated circuit device. The method can also include performing an override of the settings of the integrated circuit device based on the one or more settings of the setting record that correspond to the part number of the integrated circuit device. Various other methods and systems are also disclosed.
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公开(公告)号：US12272000B2
公开(公告)日：2025-04-08
申请号：US17853136
申请日：2022-06-29
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Kiia K. Kallio , Jan Achrenius
Abstract: Concurrently with performing a visibility pass to generate visibility data for two or more bins of an image, a processing system determines whether a primitive to be rendered covers at least a predetermined threshold percentage of a tile of the image. In response to the primitive coving at least the predetermined threshold percentage of the tile, the processing system stores the depth data of the primitive in a depth buffer for pixel-based rendering. In response to the primitive not covering at least the predetermined threshold percentage of the tile, the processing system fuses the primitive with one or more preceding primitives sharing an edge with the primitive in the tile to generate a fused primitive. In response to the fused primitive being valid in the tile, the processing system passes the depth data of the fused primitive to the depth buffer.
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Patent Agency Ranking
公开(公告)号：US12271627B2
公开(公告)日：2025-04-08
申请号：US17937292
申请日：2022-09-30
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Michael John Austin , Dmitri Tikhostoup
IPC: G06F3/06
Abstract: An apparatus and method for efficiently managing performance among multiple integrated circuits in separate semiconductor chips. In various implementations, a computing system includes at least a first processing node and a second processing node. While processing tasks, the first processing node accesses a first memory and the second processing node accesses a second memory. A first communication channel transfers data between the first and second processing nodes. The first processing node accesses the second memory using a second communication channel different from the first communication channel and supports point-to-point communication. The second memory services access requests from the first and second processing nodes as the access requests are received while foregoing access conflict detection. The first processing node accesses the second memory after a particular amount of time has elapsed after reception of an indication from the second processing node specifying that a particular task has begun.
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公开(公告)号：US20250113153A1
公开(公告)日：2025-04-03
申请号：US18374739
申请日：2023-09-29
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Carl Kittredge Wakeland , Uma Sankara Rao Balla
Abstract: A processing system includes a hardware synchronizer to synchronize the transmission of audio data from multiple I2S controllers of a processing system to one or more audio codecs. In some embodiments, each of the I2S controllers receives audio data from one or more audio data sources and stores the audio data at a buffer associated with the controller. The hardware synchronizer initiates synchronized transmission of the audio data from the plurality of controllers to the one or more codecs in response to the buffer associated with each controller being filled to a predetermined level. In some embodiments, until the controllers begin transmission of the audio data, the controllers transmit mute (null) data to the one or more codecs such that the one or more codecs receives a frame start followed by null data for each frame.
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公开(公告)号：US20250112639A1
公开(公告)日：2025-04-03
申请号：US18478892
申请日：2023-09-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Wei Han , Meeta Surendramohan Srivastav , LiLi Chen , Indrani Paul
Abstract: An apparatus can include: a processor; a voltage regulator configured to provide a processor voltage and a processor current to the processor; and a voltage regulator controller that can include a current sensor comprising an analog-to-digital converter (ADC) having an ADC input range and configured to provide current data based on an ADC input voltage, and a configuration manager configured to receive processor power data and adjust the ADC input range based on the processor power data. Various other methods, systems, and computer-readable media are also disclosed.
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公开(公告)号：US20250111586A1
公开(公告)日：2025-04-03
申请号：US18477871
申请日：2023-09-29
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Abstract: A technique for performing ray tracing operations is provided. The technique includes for a ray being tested for intersection with geometry associated with a bounding volume hierarchy, traversing to a pre-filtering node that includes information for filtering out triangles of a leaf node of the bounding volume hierarchy; evaluating a quantized ray that corresponds to the ray against quantized triangles of the pre-filtering node to filter out one or more triangles of the leaf node from consideration; and testing the triangles of the leaf node that are not filtered out and not testing the triangles of the leaf node that are filtered out.
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公开(公告)号：US20250111461A1
公开(公告)日：2025-04-03
申请号：US18374299
申请日：2023-09-28
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Alexander Fuad Ashkar , Guennadi Riguer , Nishank Pathak
IPC: G06T1/20
Abstract: A processing system includes two or more graphics cores each disposed on respective dies and configured for concurrent processing of command packets. To this end, the processing system is configured to determine two or more command partitions associated with a command packet and to assign each command partition to a graphics core. Each graphics core then executes the same command packet by only performing instructions of the command packet associated with the command partitions assigned to the graphics core. Further, after executing an instructions of the command packet based on one or more assigned partitions, each graphics core adjusts one or more counters used to synchronize the execution of the command packet across the graphics cores.
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