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    Adaptive audio mixing
    1.
    发明授权
    Adaptive audio mixing 有权

    公开(公告)号：US11839815B2

    公开(公告)日：2023-12-12

    申请号：US17132827

    申请日：2020-12-23

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Carl Kittredge Wakeland ,  Mehdi Saeedi ,  Thomas Daniel Perry ,  Gabor Sines

    IPC: A63F13/67 ,  A63F13/79 ,  A63F13/54 ,  G06N3/08 ,  G06F16/635 ,  A63F13/428 ,  G06F3/01 ,  G11B27/02

    CPC classification number: A63F13/54 ,  A63F13/428 ,  G06F3/011 ,  G06F3/017 ,  G06N3/08 ,  G11B27/02 ,  A63F2300/105 ,  A63F2300/6081

    Abstract: Systems, apparatuses, and methods for performing adaptive audio mixing are disclosed. A trained neural network dynamically selects and mixes pre-recorded, human-composed music stems that are composed as mutually compatible sets. Stem and track selection, volume mixing, filtering, dynamic compression, acoustical/reverberant characteristics, segues, tempo, beat-matching and crossfading parameters generated by the neural network are inferred from the game scene characteristics and other dynamically changing factors. The trained neural network selects an artist's pre-recorded stems and mixes the stems in real-time in unique ways to dynamically adjust and modify background music based on factors such as game scenario, the unique storyline of the player, scene elements, the player's profile, interest, and performance, adjustments made to game controls (e.g., music volume), number of viewers, received comments, player's popularity, player's native language, player's presence, and/or other factors. The trained neural network creates unique music that dynamically varies according to real-time circumstances.

    ADAPTIVE AUDIO MIXING
    2.
    发明申请
    ADAPTIVE AUDIO MIXING 有权

    公开(公告)号：US20220193549A1

    公开(公告)日：2022-06-23

    申请号：US17132827

    申请日：2020-12-23

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Carl Kittredge Wakeland ,  Mehdi Saeedi ,  Thomas Daniel Perry ,  Gabor Sines

    IPC: A63F13/54 ,  A63F13/428 ,  G06F3/01 ,  G11B27/02 ,  G06N3/08

    Abstract: Systems, apparatuses, and methods for performing adaptive audio mixing are disclosed. A trained neural network dynamically selects and mixes pre-recorded, human-composed music stems that are composed as mutually compatible sets. Stem and track selection, volume mixing, filtering, dynamic compression, acoustical/reverberant characteristics, segues, tempo, beat-matching and crossfading parameters generated by the neural network are inferred from the game scene characteristics and other dynamically changing factors. The trained neural network selects an artist's pre-recorded stems and mixes the stems in real-time in unique ways to dynamically adjust and modify background music based on factors such as game scenario, the unique storyline of the player, scene elements, the player's profile, interest, and performance, adjustments made to game controls (e.g., music volume), number of viewers, received comments, player's popularity, player's native language, player's presence, and/or other factors. The trained neural network creates unique music that dynamically varies according to real-time circumstances.

    SYNCHRONIZED AUDIO STREAMING FROM MULTIPLE CONTROLLERS
    3.
    发明申请
    SYNCHRONIZED AUDIO STREAMING FROM MULTIPLE CONTROLLERS 有权

    公开(公告)号：US20250113153A1

    公开(公告)日：2025-04-03

    申请号：US18374739

    申请日：2023-09-29

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Carl Kittredge Wakeland ,  Uma Sankara Rao Balla

    IPC: H04S3/00 ,  G06F3/16

    Abstract: A processing system includes a hardware synchronizer to synchronize the transmission of audio data from multiple I2S controllers of a processing system to one or more audio codecs. In some embodiments, each of the I2S controllers receives audio data from one or more audio data sources and stores the audio data at a buffer associated with the controller. The hardware synchronizer initiates synchronized transmission of the audio data from the plurality of controllers to the one or more codecs in response to the buffer associated with each controller being filled to a predetermined level. In some embodiments, until the controllers begin transmission of the audio data, the controllers transmit mute (null) data to the one or more codecs such that the one or more codecs receives a frame start followed by null data for each frame.

    Low power and low latency GPU coprocessor for persistent computing
    4.
    发明授权
    Low power and low latency GPU coprocessor for persistent computing 有权

    公开(公告)号：US11625807B2

    公开(公告)日：2023-04-11

    申请号：US17181300

    申请日：2021-02-22

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Jiasheng Chen ,  Timour Paltashev ,  Alexander Lyashevsky ,  Carl Kittredge Wakeland ,  Michael J. Mantor

    IPC: G06T1/20 ,  G06F9/54 ,  G06F9/38 ,  G06T1/60

    Abstract: Systems, apparatuses, and methods for implementing a graphics processing unit (GPU) coprocessor are disclosed. The GPU coprocessor includes a SIMD unit with the ability to self-schedule sub-wave procedures based on input data flow events. A host processor sends messages targeting the GPU coprocessor to a queue. In response to detecting a first message in the queue, the GPU coprocessor schedules a first sub-task for execution. The GPU coprocessor includes an inter-lane crossbar and intra-lane biased indexing mechanism for a vector general purpose register (VGPR) file. The VGPR file is split into two files. The first VGPR file is a larger register file with one read port and one write port. The second VGPR file is a smaller register file with multiple read ports and one write port. The second VGPR introduces the ability to co-issue more than one instruction per clock cycle.

    BOOT RAM FOR SAFETY CRITICAL DOMAIN
    5.
    发明申请
    BOOT RAM FOR SAFETY CRITICAL DOMAIN 有权

    公开(公告)号：US20250110750A1

    公开(公告)日：2025-04-03

    申请号：US18375294

    申请日：2023-09-29

    Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

    Inventor： Andy Sung ,  Carl Kittredge Wakeland ,  Gregory B. Shippen ,  Kaushal Amolak Sanghai ,  Uma Sankara Rao Balla ,  Balatripura S. Chavali

    IPC: G06F9/4401

    Abstract: A processing system stores a boot image for a critical domain of a system-on-a-chip (SOC) at a bank of a static random-access memory (SRAM) that is shared by the critical domain and a non-critical domain and that is powered independently from the non-critical domain. The SOC includes a secure processor that loads the boot image to the bank of the SRAM and then blocks subsequent write access to the bank. Because the critical domain is powered independently from the non-critical domain, the bank of the SRAM retains the boot image without regard to the power state of the non-critical domain. In addition, the critical domain implements a boot process that is decoupled from a CPU at the non-critical domain, ensuring that the critical domain can initiate a re-boot sequence even if the non-critical domain is not powered.

    LOW POWER AND LOW LATENCY GPU COPROCESSOR FOR PERSISTENT COMPUTING
    6.
    发明申请
    LOW POWER AND LOW LATENCY GPU COPROCESSOR FOR PERSISTENT COMPUTING 有权

    公开(公告)号：US20210201439A1

    公开(公告)日：2021-07-01

    申请号：US17181300

    申请日：2021-02-22

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Jiasheng Chen ,  Timour Paltashev ,  Alexander Lyashevsky ,  Carl Kittredge Wakeland ,  Michael J. Mantor

    IPC: G06T1/20 ,  G06F9/54 ,  G06F9/38 ,  G06T1/60

    Abstract: Systems, apparatuses, and methods for implementing a graphics processing unit (GPU) coprocessor are disclosed. The GPU coprocessor includes a SIMD unit with the ability to self-schedule sub-wave procedures based on input data flow events. A host processor sends messages targeting the GPU coprocessor to a queue. In response to detecting a first message in the queue, the GPU coprocessor schedules a first sub-task for execution. The GPU coprocessor includes an inter-lane crossbar and intra-lane biased indexing mechanism for a vector general purpose register (VGPR) file. The VGPR file is split into two files. The first VGPR file is a larger register file with one read port and one write port. The second VGPR file is a smaller register file with multiple read ports and one write port. The second VGPR introduces the ability to co-issue more than one instruction per clock cycle.

    ERROR DETECTION FOR SRAM USED IN A SAFETY-CRITICAL DOMAIN
    8.
    发明申请
    ERROR DETECTION FOR SRAM USED IN A SAFETY-CRITICAL DOMAIN 有权

    公开(公告)号：US20250157561A1

    公开(公告)日：2025-05-15

    申请号：US18389056

    申请日：2023-11-13

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： Uma Sankara Rao Balla ,  Carl Kittredge Wakeland ,  Kaushal Amolak Sanghai ,  Balatripura S. Chavali ,  Andy Sung

    IPC: G11C29/42

    Abstract: A system on a chip (SOC) includes a critical domain including components configured to perform critical operations and a non-critical domain including components configured to perform non-critical operations. To help perform such operations, the critical domain and non-critical domain share a static random-access memory (SRAM) that includes a first subset of memory banks assigned to the critical domain and a second subset of memory banks assigned to the non-critical domain. The SOC further includes a memory scrubbing circuitry configured to sequentially check each memory bank of the SRAM for errors. To this end, the memory scrubbing circuitry is configured to check a respective memory bank for errors each time an event trigger occurs by implementing one or more error correction codes.

    Low power and low latency GPU coprocessor for persistent computing
    9.
    发明授权
    Low power and low latency GPU coprocessor for persistent computing 有权

    公开(公告)号：US10929944B2

    公开(公告)日：2021-02-23

    申请号：US15360057

    申请日：2016-11-23

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Jiasheng Chen ,  Timour Paltashev ,  Alexander Lyashevsky ,  Carl Kittredge Wakeland ,  Michael J. Mantor

    IPC: G06T1/20 ,  G06F9/54 ,  G06F9/38 ,  G06T1/60

    Abstract: Systems, apparatuses, and methods for implementing a graphics processing unit (GPU) coprocessor are disclosed. The GPU coprocessor includes a SIMD unit with the ability to self-schedule sub-wave procedures based on input data flow events. A host processor sends messages targeting the GPU coprocessor to a queue. In response to detecting a first message in the queue, the GPU coprocessor schedules a first sub-task for execution. The GPU coprocessor includes an inter-lane crossbar and intra-lane biased indexing mechanism for a vector general purpose register (VGPR) file. The VGPR file is split into two files. The first VGPR file is a larger register file with one read port and one write port. The second VGPR file is a smaller register file with multiple read ports and one write port. The second VGPR introduces the ability to co-issue more than one instruction per clock cycle.

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