公开(公告)号：US20120187397A1

公开(公告)日：2012-07-26

申请号：US13356012

申请日：2012-01-23

Applicant: Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Toshihiko SAITO ,  Takehisa HATANO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Junichi KOEZUKA ,  Yuichi SATO ,  Shinji OHNO

Inventor： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Toshihiko SAITO ,  Takehisa HATANO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Junichi KOEZUKA ,  Yuichi SATO ,  Shinji OHNO

IPC: H01L29/786

CPC classification number: H01L29/66969 ,  H01L21/02488 ,  H01L21/02565 ,  H01L27/1225 ,  H01L29/786 ,  H01L29/78606 ,  H01L29/7869

Abstract: A semiconductor device which includes an oxide semiconductor and has favorable electrical characteristics is provided. In the semiconductor device, an oxide semiconductor film and an insulating film are formed over a substrate. Side surfaces of the oxide semiconductor film are in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. A gate insulating film is formed on and in contact with the oxide semiconductor film. A gate electrode with sidewall insulating films is formed over the gate insulating film. A source electrode and a drain electrode are formed in contact with the oxide semiconductor film and the insulating film.

Abstract translation: 提供了包括氧化物半导体并且具有良好的电特性的半导体器件。 在半导体器件中，在衬底上形成氧化物半导体膜和绝缘膜。 氧化物半导体膜的侧面与绝缘膜接触。 氧化物半导体膜包括沟道形成区域和包含掺杂剂的区域，沟道形成区域夹在其间。 栅极绝缘膜与氧化物半导体膜形成并接触。 在栅绝缘膜上形成具有侧壁绝缘膜的栅电极。 源电极和漏电极形成为与氧化物半导体膜和绝缘膜接触。

公开(公告)号：US08143118B2

公开(公告)日：2012-03-27

申请号：US12073618

申请日：2008-03-07

Applicant: Hideto Ohnuma ,  Atsuo Isobe ,  Hiromichi Godo

Inventor： Hideto Ohnuma ,  Atsuo Isobe ,  Hiromichi Godo

IPC: H01L21/84

CPC classification number: H01L29/78696 ,  H01L21/0237 ,  H01L21/02675 ,  H01L21/02691 ,  H01L27/1281

Abstract: A semiconductor device having a highly responsive thin film transistor (TFT) with low subthreshold swing and suppressed decrease in the on-state current and a manufacturing method thereof are demonstrated. The TFT of the present invention is characterized by its semiconductor layer where the thickness of the source region or the drain region is larger than that of the channel formation region. Manufacture of the TFT is readily achieved by the formation of an amorphous semiconductor layer on a projection portion and a depression portion, which is followed by subjecting the melting process of the semiconductor layer, resulting in the formation of a crystalline semiconductor layer having different thicknesses. Selective addition of impurity to the thick portion of the semiconductor layer provides a semiconductor layer in which the channel formation region is thinner than the source or drain region.

Abstract translation: 示出了具有低亚阈值摆动和抑制导通电流下降的高响应性薄膜晶体管（TFT）的半导体器件及其制造方法。 本发明的TFT的特征在于其源极区域或漏极区域的厚度大于沟道形成区域的厚度的半导体层。 通过在突起部分和凹陷部分上形成非晶半导体层来容易地实现TFT的制造，随后对半导体层进行熔化处理，形成具有不同厚度的晶体半导体层。 选择性地向半导体层的厚部分添加杂质提供了沟道形成区域比源区或漏区更薄的半导体层。

公开(公告)号：US20120032236A1

公开(公告)日：2012-02-09

申请号：US13277489

申请日：2011-10-20

Applicant: Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Hiromichi GODO ,  Yutaka OKAZAKI

Inventor： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Hiromichi GODO ,  Yutaka OKAZAKI

IPC: H01L27/092

CPC classification number: H01L27/1266 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/433 ,  H01L23/481 ,  H01L23/552 ,  H01L27/0688 ,  H01L27/1214 ,  H01L27/1229 ,  H01L29/7843 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/16152 ,  H01L2924/16195

Abstract: An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.

Abstract translation: 目的是在具有SOI结构的半导体器件中实现高性能和低功耗。 此外，另一个目的是提供一种具有更高集成度的高性能半导体元件的半导体器件。 半导体器件使得多个n沟道场效应晶体管和p沟道场效应晶体管层叠在其间具有绝缘表面的衬底之间的层间绝缘层。 通过控制由于具有应力的绝缘膜，半导体层的平面取向和沟道长度方向的晶轴引起的半导体层的失真，n沟道场效应晶体管和 可以减小p沟道场效应晶体管，由此n沟道场效应晶体管的电流驱动能力和响应速度与p沟道场效应相当。

公开(公告)号：US20120018808A1

公开(公告)日：2012-01-26

申请号：US13251641

申请日：2011-10-03

Applicant: Atsuo ISOBE

Inventor： Atsuo ISOBE

IPC: H01L27/12 ,  H01L21/30

CPC classification number: H01L27/088 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/78603

Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. A semiconductor device comprises a first single-crystal semiconductor layer including a first channel formation region and a first impurity region over a substrate having an insulating surface, a first gate insulating layer over the first single-crystal semiconductor layer, a gate electrode over the first gate insulating layer, a first interlayer insulating layer over the first gate insulating layer, a second gate insulating layer over the gate electrode and the first interlayer insulating layer, and a second single-crystal semiconductor layer including a second channel formation region and a second impurity region over the second gate insulating layer. The first channel formation region, the gate electrode, and the second channel formation region are overlapped with each other.

Abstract translation: 提供半导体器件和半导体器件的制造方法。 半导体器件包括：第一单晶半导体层，包括在具有绝缘表面的衬底上的第一沟道形成区和第一杂质区;在第一单晶半导体层上方的第一栅绝缘层，第一单晶半导体层上的栅电极 栅极绝缘层，第一栅极绝缘层上的第一层间绝缘层，栅极电极和第一层间绝缘层之上的第二栅极绝缘层，以及包括第二沟道形成区域和第二杂质的第二单晶半导体层 区域。 第一沟道形成区域，栅极电极和第二沟道形成区域彼此重叠。

公开(公告)号：US08044464B2

公开(公告)日：2011-10-25

申请号：US12209739

申请日：2008-09-12

Applicant: Shunpei Yamazaki ,  Atsuo Isobe ,  Hiromichi Godo ,  Yutaka Okazaki

Inventor： Shunpei Yamazaki ,  Atsuo Isobe ,  Hiromichi Godo ,  Yutaka Okazaki

IPC: H01L27/01

CPC classification number: H01L27/1266 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/433 ,  H01L23/481 ,  H01L23/552 ,  H01L27/0688 ,  H01L27/1214 ,  H01L27/1229 ,  H01L29/7843 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/16152 ,  H01L2924/16195

Abstract: An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.

Abstract translation: 目的是在具有SOI结构的半导体器件中实现高性能和低功耗。 此外，另一个目的是提供一种具有更高集成度的高性能半导体元件的半导体器件。 半导体器件使得多个n沟道场效应晶体管和p沟道场效应晶体管层叠在其间具有绝缘表面的衬底之间的层间绝缘层。 通过控制由于具有应力的绝缘膜，半导体层的平面取向和沟道长度方向的晶轴引起的半导体层的失真，n沟道场效应晶体管与 可以减小p沟道场效应晶体管，由此n沟道场效应晶体管的电流驱动能力和响应速度与p沟道场效应相当。

公开(公告)号：US08008140B2

公开(公告)日：2011-08-30

申请号：US11256086

申请日：2005-10-24

Applicant: Mayumi Yamaguchi ,  Atsuo Isobe ,  Satoru Saito

Inventor： Mayumi Yamaguchi ,  Atsuo Isobe ,  Satoru Saito

IPC: H01L21/00

CPC classification number: H01L27/1266 ,  H01L27/1214 ,  H01L27/127 ,  H01L29/66757 ,  H01L29/78621 ,  H01L2029/7863

Abstract: It is an object of the present invention to manufacture a TFT having a small-sized LDD region in a process with a few processing step and to manufacture TFTs each having a structure depending on each circuit separately. According to the present invention, a gate electrode is a multilayer, and a hat-shaped gate electrode is formed by having the longer gate length of a lower-layer gate electrode than that of an upper-layer gate electrode. At this time, only the upper-layer gate electrode is etched by using a resist recess width to form the hat-shaped gate electrode. Accordingly, an LDD region can be formed also in a fine TFT; thus, TFTs having a structure depending on each circuit can be manufactured separately.

Abstract translation: 本发明的目的是在具有少量加工步骤的工艺中制造具有小尺寸LDD区域的TFT，并且制造各自具有依赖于每个电路的结构的TFT。 根据本发明，栅电极是多层的，并且通过使下层栅电极的栅极长度比上层栅电极的栅极长度长，形成帽形栅电极。 此时，仅通过使用抗蚀剂凹部宽度来蚀刻上层栅电极，形成帽状栅电极。 因此，也可以在精细TFT中形成LDD区域; 因此，可以分别制造具有取决于每个电路的结构的TFT。

公开(公告)号：US07982250B2

公开(公告)日：2011-07-19

申请号：US12209696

申请日：2008-09-12

Applicant: Shunpei Yamazaki ,  Atsuo Isobe ,  Hiromichi Godo ,  Yutaka Okazaki

Inventor： Shunpei Yamazaki ,  Atsuo Isobe ,  Hiromichi Godo ,  Yutaka Okazaki

IPC: H01L27/12

CPC classification number: H01L21/8221 ,  H01L27/0688 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/13099 ,  H01L2224/80001

Abstract: A semiconductor device is demonstrated in which a plurality of field-effect transistors is stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. Each of the plurality of filed-effect transistors has a semiconductor layer which is prepared by a process including separation of the semiconductor layer from a semiconductor substrate followed by bonding thereof over the substrate. Each of the plurality of field-effect transistors is covered with an insulating film which provides distortion of the semiconductor layer. Furthermore, the crystal axis of the semiconductor layer, which is parallel to the crystal plane thereof, is set to a channel length direction of the semiconductor layer, which enables production of the semiconductor device with high performance and low power consumption having an SOI structure.

Abstract translation: 示出了一种半导体器件，其中在具有绝缘表面的衬底上层叠多个场效应晶体管，层间绝缘层介于其间。 多个场效应晶体管中的每一个具有半导体层，该半导体层通过包括将半导体层与半导体衬底分离并随后在衬底上结合的工艺制备。 多个场效应晶体管中的每一个被覆盖有提供半导体层失真的绝缘膜。 此外，将半导体层的与其晶面平行的晶轴设定为半导体层的沟道长度方向，能够制造具有SOI结构的高性能，低功耗的半导体器件。

公开(公告)号：US20110114964A1

公开(公告)日：2011-05-19

申请号：US13012448

申请日：2011-01-24

Applicant: Hiroshi SHIBATA ,  Atsuo ISOBE

Inventor： Hiroshi SHIBATA ,  Atsuo ISOBE

IPC: H01L33/16

CPC classification number: H01L27/1255 ,  G02F1/133345 ,  G02F1/13454 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136227 ,  G02F1/136277 ,  G02F1/136286 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/3244 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3276 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/78633

Abstract: To provide a liquid crystal display device having high quality display by obtaining a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a different layer from a gate electrode and the capacitor wiring is arranged so as to be parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of a neighboring pixel can be avoided, whereby obtaining satisfactory display images.

Abstract translation: 为了提供一种通过在确保足够的存储电容器（Cs）的同时获得高开口率而具有高质量显示的液晶显示装置，并且同时通过分散电容器布线的负载（像素写入电流） 及时有效减轻负荷。 扫描线形成在与栅电极不同的层上，电容布线与信号线平行。 每个像素通过电介质连接到单独独立的电容器布线。 因此，可以避免由相邻像素的写入电流引起的电容器布线的电位变化，从而获得令人满意的显示图像。

公开(公告)号：US20100297809A1

公开(公告)日：2010-11-25

申请号：US12850652

申请日：2010-08-05

Applicant: Ryota IMAHAYASHI ,  Shinobu FURUKAWA ,  Atsuo ISOBE ,  Yasuyuki ARAI ,  Shunpei YAMAZAKI

Inventor： Ryota IMAHAYASHI ,  Shinobu FURUKAWA ,  Atsuo ISOBE ,  Yasuyuki ARAI ,  Shunpei YAMAZAKI

IPC: H01L51/40

CPC classification number: H01L51/0512 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/31683 ,  H01L51/0002 ,  H01L51/0055 ,  H01L51/0525 ,  H01L51/0541 ,  H01L51/0545 ,  H01L51/0566

Abstract: It is an object to form a high quality gate insulating film which is dense and has a strong insulation resistance property, and to propose a high reliable organic transistor in which a tunnel leakage current is little. One mode of the organic transistor of the present invention has a step of forming the gate insulating film by forming the conductive layer which becomes the gate electrode activating oxygen (or gas including oxygen) or nitrogen (or gas including nitrogen) or the like using dense plasma in which density of electron is 1011 cm−3 or more, and electron temperature is a range of 0.2 eV to 2.0 eV with plasma activation, and reacting directly with a portion of the conductive layer which becomes the gate electrode to be insulated.

Abstract translation: 本发明的目的是形成致密且具有很强绝缘电阻特性的高质量栅极绝缘膜，并且提出了隧道泄漏电流很小的高可靠性有机晶体管。 本发明的有机晶体管的一种模式具有如下步骤：通过使用密集的方法形成作为活化氧（或含氧气体）或氮（或含氮气体）的栅极的导电层形成栅极绝缘膜 电子密度为1011cm -3以上的等离子体，等离子体活化时电子温度为0.2eV〜2.0eV的范围，直接与成为要被绝缘的栅电极的导体层的一部分反应。

公开(公告)号：US20100187524A1

公开(公告)日：2010-07-29

申请号：US12751300

申请日：2010-03-31

Applicant: Atsuo ISOBE ,  Tamae TAKANO ,  Yasuyuki ARAI ,  Fumiko TERASAWA

Inventor： Atsuo ISOBE ,  Tamae TAKANO ,  Yasuyuki ARAI ,  Fumiko TERASAWA

IPC: H01L29/786 ,  H01L29/12 ,  H01L29/788

CPC classification number: H01L27/12 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A manufacturing method of a semiconductor device of the present invention includes the steps of forming a stacked body in which a semiconductor film, a gate insulating film, and a first conductive film are sequentially stacked over a substrate; selectively removing the stacked body to form a plurality of island-shaped stacked bodies; forming an insulating film to cover the plurality of island-shaped stacked bodies; removing a part of the insulating film to expose a surface of the first conductive film, such that a surface of the first conductive film almost coextensive with a height of the insulating film; forming a second conductive film over the first conductive film and a left part of the insulating film; forming a resist over the second conductive film; selectively removing the first conductive film and the second conductive film using the resist as a mask.

Abstract translation: 本发明的半导体器件的制造方法包括以下步骤：在衬底上依次层叠有半导体膜，栅极绝缘膜和第一导电膜的层叠体; 选择性地去除层叠体以形成多个岛状堆叠体; 形成绝缘膜以覆盖所述多个岛状堆叠体; 去除绝缘膜的一部分以暴露第一导电膜的表面，使得第一导电膜的表面几乎与绝缘膜的高度共同延伸; 在所述第一导电膜和所述绝缘膜的左部分上形成第二导电膜; 在所述第二导电膜上形成抗蚀剂; 使用抗蚀剂作为掩模选择性地去除第一导电膜和第二导电膜。