公开(公告)号：US07564042B2

公开(公告)日：2009-07-21

申请号：US11834561

申请日：2007-08-06

Applicant: Do-Haing Lee ,  Sung-Wook Hwang ,  Chul-Ho Shin

Inventor： Do-Haing Lee ,  Sung-Wook Hwang ,  Chul-Ho Shin

IPC: H05H1/02 ,  H01J3/14 ,  H01J37/08

CPC classification number: H01J37/08 ,  H01J27/024 ,  H01J37/3053 ,  H01J2237/061 ,  H01J2237/24542

Abstract: An ion beam apparatus includes a plasma chamber with a grid assembly installed at one end of the plasma chamber and a plasma sheath controller disposed between the plasma chamber and the grid assembly. The grid assembly includes first ion extraction apertures. The plasma sheath controller includes second ion extraction apertures smaller than the first ion extraction apertures. When the plasma sheath controller is used in this configuration, the surface of the plasma takes on a more planar configuration adjacent the controller so that ions, extracted from the plasma in a perpendicular direction to the plasma surface, pass cleanly through the apertures of the grid assembly rather than collide with the sidewalls of the grid assembly apertures. A semiconductor manufacturing apparatus and method for forming an ion beam are also provided.

Abstract translation: 离子束装置包括等离子体室，其中安装在等离子体室的一端的栅格组件和设置在等离子体室和栅格组件之间的等离子体鞘控制器。 栅格组件包括第一离子提取孔。 等离子体鞘控制器包括比第一离子提取孔小的第二离子提取孔。 当在该构造中使用等离子体鞘控制器时，等离子体的表面具有与控制器相邻的更平面的配置，使得从垂直于等离子体表面的方向从等离子体提取的离子通过网格的孔 组件而不是与栅格组件孔的侧壁碰撞。 还提供了用于形成离子束的半导体制造装置和方法。

公开(公告)号：US07446325B2

公开(公告)日：2008-11-04

申请号：US11341558

申请日：2006-01-30

Applicant: Sung-Wook Hwang ,  Chul-Ho Shin

Inventor： Sung-Wook Hwang ,  Chul-Ho Shin

IPC: H01S3/00

CPC classification number: H01J37/32422 ,  H05H3/02

Abstract: Example embodiments of the present invention provide a reflector for generating a neutral beam and a substrate processing apparatus including the same. The reflector may include at least one reflecting plate including a reflecting layer onto which an ion beam collides and a supporting layer. The reflecting layer may reflect and convert the ion beam into a neutral beam, and the supporting layer may reduce thermal deformation of the reflecting layer.

Abstract translation: 本发明的示例性实施例提供了一种用于产生中性光束的反射器和包括该反射体的基板处理设备。 反射器可以包括至少一个反射板，该反射板包括反射层，离子束在其上碰撞和支撑层。 反射层可以将离子束反射并转换成中性光束，并且支撑层可以减小反射层的热变形。

公开(公告)号：US20080179546A1

公开(公告)日：2008-07-31

申请号：US11834561

申请日：2007-08-06

Applicant: Do-Haing LEE ,  Sung-Wook HWANG ,  Chul-Ho SHIN

Inventor： Do-Haing LEE ,  Sung-Wook HWANG ,  Chul-Ho SHIN

IPC: H01J37/08

CPC classification number: H01J37/08 ,  H01J27/024 ,  H01J37/3053 ,  H01J2237/061 ,  H01J2237/24542

Abstract: An ion beam apparatus includes a plasma chamber with a grid assembly installed at one end of the plasma chamber and a plasma sheath controller disposed between the plasma chamber and the grid assembly. The grid assembly includes first ion extraction apertures. The plasma sheath controller includes second ion extraction apertures smaller than the first ion extraction apertures. When the plasma sheath controller is used in this configuration, the surface of the plasma takes on a more planar configuration adjacent the controller so that ions, extracted from the plasma in a perpendicular direction to the plasma surface, pass cleanly through the apertures of the grid assembly rather than collide with the sidewalls of the grid assembly apertures. A semiconductor manufacturing apparatus and method for forming an ion beam are also provided.

Abstract translation: 离子束装置包括等离子体室，其中安装在等离子体室的一端的栅格组件和设置在等离子体室和栅格组件之间的等离子体鞘控制器。 栅格组件包括第一离子提取孔。 等离子体鞘控制器包括比第一离子提取孔小的第二离子提取孔。 当在该构造中使用等离子体鞘控制器时，等离子体的表面具有与控制器相邻的更平面的配置，使得从垂直于等离子体表面的方向从等离子体提取的离子通过网格的孔 组件而不是与栅格组件孔的侧壁碰撞。 还提供了用于形成离子束的半导体制造装置和方法。

公开(公告)号：US20060219887A1

公开(公告)日：2006-10-05

申请号：US11341558

申请日：2006-01-30

Applicant: Sung-Wook Hwang ,  Chul-Ho Shin

Inventor： Sung-Wook Hwang ,  Chul-Ho Shin

IPC: H05H3/02

CPC classification number: H01J37/32422 ,  H05H3/02

Abstract: Example embodiments of the present invention provide a reflector for generating a neutral beam and a substrate processing apparatus including the same. The reflector may include at least one reflecting plate including a reflecting layer onto which an ion beam collides and a supporting layer. The reflecting layer may reflect and convert the ion beam into a neutral beam, and the supporting layer may reduce thermal deformation of the reflecting layer.

Abstract translation: 本发明的示例性实施例提供了一种用于产生中性光束的反射器和包括该反射体的基板处理设备。 反射器可以包括至少一个反射板，该反射板包括反射层，离子束在其上碰撞和支撑层。 反射层可以将离子束反射并转换成中性光束，并且支撑层可以减小反射层的热变形。

公开(公告)号：US20110143532A1

公开(公告)日：2011-06-16

申请号：US12801013

申请日：2010-05-17

Applicant: Keun-Hee Bai ,  Chul-Ho Shin ,  Shin-Hye Kim ,  Sang-Kuk Kim

Inventor： Keun-Hee Bai ,  Chul-Ho Shin ,  Shin-Hye Kim ,  Sang-Kuk Kim

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/31111 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10888

Abstract: In a method of forming a semiconductor cell structure, a first insulating layer may be formed on a semiconductor substrate. A connection pattern may be formed in the first insulating layer. Second and third insulating layers may be sequentially formed on the connection pattern. The third insulating layer may be etched at least twice and the second insulating layer may be etched at least once to form a through hole in the second and third insulating layers. The through hole may expose the connection pattern.

Abstract translation: 在形成半导体单元结构的方法中，可以在半导体衬底上形成第一绝缘层。 可以在第一绝缘层中形成连接图案。 第二和第三绝缘层可以顺序形成在连接图案上。 可以将第三绝缘层蚀刻至少两次，并且可以蚀刻第二绝缘层至少一次以在第二和第三绝缘层中形成通孔。 通孔可能暴露连接图案。

公开(公告)号：US5317534A

公开(公告)日：1994-05-31

申请号：US981488

申请日：1992-11-25

Applicant: Jeong-Hyeok Choi ,  Chul-Ho Shin

Inventor： Jeong-Hyeok Choi ,  Chul-Ho Shin

IPC: H01L21/8246 ,  H01L27/112 ,  G11C11/40

CPC classification number: H01L27/1126 ,  H01L27/112

Abstract: A method for manufacturing highly integrated NAND and NOR logic mask read only memory (MROM) devices is disclosed. Over the top surface of a semiconductor substrate, where a first polysilicon layer is formed, a pattern of a gate electrode is formed along a word line in the order of odd numbers or even numbers. Next, an insulation layer having a thickness of a submicron range is formed over the top surface of the substrate. And then a photoresist is covered and an etch back process is performed. Thereafter, the exposed insulation layer caused by the etch back process and the polysilicon layer are selectively etched to form a word line spacing corresponding to a thickness of the insulation layer. Thus, spacing between adjacent word lines can be minimized and a process margin can be sufficiently ensured.

Abstract translation: 公开了一种用于制造高度集成的NAND和NOR逻辑掩模只读存储器（MROM）器件的方法。 在形成第一多晶硅层的半导体衬底的顶表面上，沿着字线以奇数或偶数的顺序形成栅电极的图案。 接下来，在衬底的顶表面上形成具有亚微米范围厚度的绝缘层。 然后覆盖光致抗蚀剂并执行回蚀刻工艺。 此后，选择性地蚀刻由回蚀处理和多晶硅层引起的暴露的绝缘层，以形成对应于绝缘层的厚度的字线间距。 因此，可以最小化相邻字线之间的间隔，并且可以充分地确保处理余量。

公开(公告)号：US08318412B2

公开(公告)日：2012-11-27

申请号：US12871251

申请日：2010-08-30

Applicant: Tokashiki Ken ,  Chul-ho Shin ,  Sang-Kuk Kim ,  Do-haing Lee ,  Dong-seok Lee

Inventor： Tokashiki Ken ,  Chul-ho Shin ,  Sang-Kuk Kim ,  Do-haing Lee ,  Dong-seok Lee

IPC: G03F7/26

CPC classification number: H01L21/31138 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/10855

Abstract: A semiconductor device is manufactured by a method including processes of trimming and molding resist patterns. A resist layer formed on a substrate is exposed and developed to form the resist patterns. The resist patterns are trimmed using a first gas plasma to change the profiles of the resist patterns. Widths of the trimmed resist patterns are increased using a second gas plasma to form processed resist patterns.

Abstract translation: 通过包括修整和成型抗蚀剂图案的工艺的方法制造半导体器件。 形成在基板上的抗蚀剂层被曝光和显影以形成抗蚀剂图案。 使用第一气体等离子体来修整抗蚀剂图案以改变抗蚀剂图案的轮廓。 使用第二气体等离子体增加修整的抗蚀剂图案的宽度以形成经处理的抗蚀剂图案。

公开(公告)号：US08252655B2

公开(公告)日：2012-08-28

申请号：US12801013

申请日：2010-05-17

Applicant: Keun-Hee Bai ,  Chul-Ho Shin ,  Shin-Hye Kim ,  Sang-Kuk Kim

Inventor： Keun-Hee Bai ,  Chul-Ho Shin ,  Shin-Hye Kim ,  Sang-Kuk Kim

IPC: H01L21/8228

CPC classification number: H01L21/76802 ,  H01L21/31111 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10888

Abstract: In a method of forming a semiconductor cell structure, a first insulating layer may be formed on a semiconductor substrate. A connection pattern may be formed in the first insulating layer. Second and third insulating layers may be sequentially formed on the connection pattern. The third insulating layer may be etched at least twice and the second insulating layer may be etched at least once to form a through hole in the second and third insulating layers. The through hole may expose the connection pattern.

Abstract translation: 在形成半导体单元结构的方法中，可以在半导体衬底上形成第一绝缘层。 可以在第一绝缘层中形成连接图案。 第二和第三绝缘层可以顺序形成在连接图案上。 可以将第三绝缘层蚀刻至少两次，并且可以蚀刻第二绝缘层至少一次以在第二和第三绝缘层中形成通孔。 通孔可能暴露连接图案。

公开(公告)号：US20120040508A1

公开(公告)日：2012-02-16

申请号：US13188981

申请日：2011-07-22

Applicant: Gyu-Hwan Oh ,  Sung-Lae Cho ,  Byoung-Jae Bae ,  Ik-Soo Kim ,  Dong-Hyun Im ,  Doo-Hwan Park ,  Kyoung-Ha Eom ,  Sung-Un Kwon ,  Chul-Ho Shin ,  Sang-Sup Jeong

Inventor： Gyu-Hwan Oh ,  Sung-Lae Cho ,  Byoung-Jae Bae ,  Ik-Soo Kim ,  Dong-Hyun Im ,  Doo-Hwan Park ,  Kyoung-Ha Eom ,  Sung-Un Kwon ,  Chul-Ho Shin ,  Sang-Sup Jeong

IPC: H01L47/00

CPC classification number: H01L45/1683 ,  H01L27/2463 ,  H01L45/06

Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.

Abstract translation: 形成基板上的导电图案。 形成具有露出导电图案的开口的绝缘层。 底部电极形成在导电图案和开口的第一侧壁上。 在底部电极和开口的第二侧壁上形成间隔物。 间隔件和底部电极形成为低于绝缘层的顶表面。 数据存储插头形成在底部电极和间隔件上。 数据存储插头具有与底部电极的侧壁对准的第一侧壁和与间隔件的侧壁对准的第二侧壁。 在数据存储插头上形成位线。

公开(公告)号：US20110159442A1

公开(公告)日：2011-06-30

申请号：US12871251

申请日：2010-08-30

Applicant: Tokashiki Ken ,  Chul-ho Shin ,  Sang-Kuk Kim ,  Do-haing Lee ,  Dong-seok Lee

Inventor： Tokashiki Ken ,  Chul-ho Shin ,  Sang-Kuk Kim ,  Do-haing Lee ,  Dong-seok Lee

IPC: G03F7/20

CPC classification number: H01L21/31138 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/10855

Abstract: A semiconductor device is manufactured by a method including processes of trimming and molding resist patterns. A resist layer formed on a substrate is exposed and developed to form the resist patterns. The resist patterns are trimmed using a first gas plasma to change the profiles of the resist patterns. Widths of the trimmed resist patterns are increased using a second gas plasma to form processed resist patterns.

Abstract translation: 通过包括修整和成型抗蚀剂图案的工艺的方法制造半导体器件。 形成在基板上的抗蚀剂层被曝光和显影以形成抗蚀剂图案。 使用第一气体等离子体来修整抗蚀剂图案以改变抗蚀剂图案的轮廓。 使用第二气体等离子体增加修整的抗蚀剂图案的宽度以形成经处理的抗蚀剂图案。