公开(公告)号：US20050194361A1

公开(公告)日：2005-09-08

申请号：US10825099

申请日：2004-04-16

Applicant: Geun-Young Yeom ,  Do-Haing Lee ,  Byoung-Jae Park

Inventor： Geun-Young Yeom ,  Do-Haing Lee ,  Byoung-Jae Park

IPC: H01L21/3065 ,  B23K9/00

CPC classification number: H01L21/3065 ,  H01J37/321 ,  H01J37/32422 ,  H01J37/3266 ,  H01L21/31116 ,  H05H3/02

Abstract: Disclosed is a neutral beam source used for etching a semiconductor device. The neutral beam source includes a plasma chamber having quartz provided at an outer wall thereof with an RF coil, a grid assembly, a reflective member, and an electromagnet arranged around the plasma chamber while surrounding the plasma chamber. Plasma density becomes high due to the magnetic field applied to the plasma chamber so that an amount of ion flux is increased.

Abstract translation: 公开了一种用于蚀刻半导体器件的中性束源。 中性束源包括具有在其外壁处设置有RF线圈的石英等离子体室，栅格组件，反射构件和围绕等离子体室围绕等离子体室的电磁体。 由于施加到等离子体室的磁场，等离子体密度变高，使得离子通量增加。

公开(公告)号：US06926799B2

公开(公告)日：2005-08-09

申请号：US10086496

申请日：2002-02-28

Applicant: Geun-young Yeom ,  Do-haing Lee ,  Min-jae Chung

Inventor： Geun-young Yeom ,  Do-haing Lee ,  Min-jae Chung

IPC: H01L21/3065 ,  C23F4/00 ,  H01J37/08 ,  H01L21/00

CPC classification number: C23F4/00 ,  H01J37/08

Abstract: A damage-free apparatus for etching the large area by using a neutral beam which can perform an etching process without causing electrical and physical damages by the use of the neutral beam is provided. The damage-free etching apparatus includes: an ion source for extracting and accelerating an ion beam having a predetermined polarity; a grid positioned at the rear of the ion source and having a plurality of grid holes through which the ion beam passes; a reflector closely attached to the grid and having a plurality of reflector holes corresponding to the grid holes in the grid, the reflector for reflecting the ion beam passed through the grid holes in the reflector holes and neutralizing the ion beam into a neutral beam; and a stage for placing a substrate to be etched in a path of the neutral beam.

Abstract translation: 提供了一种用于通过使用能够执行蚀刻工艺而不会因使用中性光束造成电和物理损坏的中性光束来蚀刻大面积的无损伤设备。 无损伤蚀刻装置包括：用于提取和加速具有预定极性的离子束的离子源; 位于离子源的后部并具有多个栅格孔的栅极，离子束通过该栅格孔; 一个靠近网格的反射器，具有对应于格栅中的栅格孔的多个反射孔，反射器用于反射通过反射孔中的栅格孔的离子束，并将离子束中和成中性光束; 以及用于将要蚀刻的衬底放置在中性光束的路径中的阶段。

公开(公告)号：US07564042B2

公开(公告)日：2009-07-21

申请号：US11834561

申请日：2007-08-06

Applicant: Do-Haing Lee ,  Sung-Wook Hwang ,  Chul-Ho Shin

Inventor： Do-Haing Lee ,  Sung-Wook Hwang ,  Chul-Ho Shin

IPC: H05H1/02 ,  H01J3/14 ,  H01J37/08

CPC classification number: H01J37/08 ,  H01J27/024 ,  H01J37/3053 ,  H01J2237/061 ,  H01J2237/24542

Abstract: An ion beam apparatus includes a plasma chamber with a grid assembly installed at one end of the plasma chamber and a plasma sheath controller disposed between the plasma chamber and the grid assembly. The grid assembly includes first ion extraction apertures. The plasma sheath controller includes second ion extraction apertures smaller than the first ion extraction apertures. When the plasma sheath controller is used in this configuration, the surface of the plasma takes on a more planar configuration adjacent the controller so that ions, extracted from the plasma in a perpendicular direction to the plasma surface, pass cleanly through the apertures of the grid assembly rather than collide with the sidewalls of the grid assembly apertures. A semiconductor manufacturing apparatus and method for forming an ion beam are also provided.

Abstract translation: 离子束装置包括等离子体室，其中安装在等离子体室的一端的栅格组件和设置在等离子体室和栅格组件之间的等离子体鞘控制器。 栅格组件包括第一离子提取孔。 等离子体鞘控制器包括比第一离子提取孔小的第二离子提取孔。 当在该构造中使用等离子体鞘控制器时，等离子体的表面具有与控制器相邻的更平面的配置，使得从垂直于等离子体表面的方向从等离子体提取的离子通过网格的孔 组件而不是与栅格组件孔的侧壁碰撞。 还提供了用于形成离子束的半导体制造装置和方法。

公开(公告)号：US20080179546A1

公开(公告)日：2008-07-31

申请号：US11834561

申请日：2007-08-06

Applicant: Do-Haing LEE ,  Sung-Wook HWANG ,  Chul-Ho SHIN

Inventor： Do-Haing LEE ,  Sung-Wook HWANG ,  Chul-Ho SHIN

IPC: H01J37/08

CPC classification number: H01J37/08 ,  H01J27/024 ,  H01J37/3053 ,  H01J2237/061 ,  H01J2237/24542

Abstract: An ion beam apparatus includes a plasma chamber with a grid assembly installed at one end of the plasma chamber and a plasma sheath controller disposed between the plasma chamber and the grid assembly. The grid assembly includes first ion extraction apertures. The plasma sheath controller includes second ion extraction apertures smaller than the first ion extraction apertures. When the plasma sheath controller is used in this configuration, the surface of the plasma takes on a more planar configuration adjacent the controller so that ions, extracted from the plasma in a perpendicular direction to the plasma surface, pass cleanly through the apertures of the grid assembly rather than collide with the sidewalls of the grid assembly apertures. A semiconductor manufacturing apparatus and method for forming an ion beam are also provided.

Abstract translation: 离子束装置包括等离子体室，其中安装在等离子体室的一端的栅格组件和设置在等离子体室和栅格组件之间的等离子体鞘控制器。 栅格组件包括第一离子提取孔。 等离子体鞘控制器包括比第一离子提取孔小的第二离子提取孔。 当在该构造中使用等离子体鞘控制器时，等离子体的表面具有与控制器相邻的更平面的配置，使得从垂直于等离子体表面的方向从等离子体提取的离子通过网格的孔 组件而不是与栅格组件孔的侧壁碰撞。 还提供了用于形成离子束的半导体制造装置和方法。

公开(公告)号：US07060931B2

公开(公告)日：2006-06-13

申请号：US10825099

申请日：2004-04-16

Applicant: Geun-Young Yeom ,  Do-Haing Lee ,  Byoung Jac Park

Inventor： Geun-Young Yeom ,  Do-Haing Lee ,  Byoung Jac Park

IPC: B23K9/00

CPC classification number: H01L21/3065 ,  H01J37/321 ,  H01J37/32422 ,  H01J37/3266 ,  H01L21/31116 ,  H05H3/02

Abstract: Disclosed is a neutral beam source used for etching a semiconductor device. The neutral beam source includes a plasma chamber having quartz provided at an outer wall thereof with an RF coil, a grid assembly, a reflective member, and an electromagnet arranged around the plasma chamber while surrounding the plasma chamber. Plasma density becomes high due to the magnetic field applied to the plasma chamber so that an amount of ion flux is increased.

Abstract translation: 公开了一种用于蚀刻半导体器件的中性束源。 中性束源包括具有在其外壁处设置有RF线圈的石英等离子体室，栅格组件，反射构件和围绕等离子体室围绕等离子体室的电磁体。 由于施加到等离子体室的磁场，等离子体密度变高，使得离子通量增加。

公开(公告)号：US20050189482A1

公开(公告)日：2005-09-01

申请号：US10814148

申请日：2004-04-01

Applicant: Geun-Young Yeom ,  Do-Haing Lee ,  Byoung Park

Inventor： Geun-Young Yeom ,  Do-Haing Lee ,  Byoung Park

IPC: H01L21/3065 ,  H05H3/02

CPC classification number: H05H3/02

Abstract: Disclosed is a 3-grid neutral beam source used for etching a semiconductor device. The 3-grid neutral beam source includes a plasma generating chamber, a grid assembly including first to third grids, which are sequentially overlapped with each other by interposing an insulation material therebetween for obtaining a great amount of ion flux at a low ion energy, and a reflective member for converting an ion beam into a neutral beam by reflecting the ion beam. The semiconductor device is prevented from being damaged due to reduced kinetic energy of ions, and an etch rate of the semiconductor device is improved.

Abstract translation: 公开了一种用于蚀刻半导体器件的3栅极中性束源。 三栅中性束源包括等离子体发生室，包括第一至第三栅极的栅格组件，其通过在其间插入绝缘材料而相互重叠，以在低离子能量下获得大量的离子通量，以及 用于通过反射离子束将离子束转换成中立光束的反射构件。 防止半导体器件由于离子的动能降低而被损坏，并且提高了半导体器件的蚀刻速率。

公开(公告)号：US06874443B2

公开(公告)日：2005-04-05

申请号：US10086497

申请日：2002-02-28

Applicant: Geun-young Yeom ,  Min-jae Chung ,  Do-haing Lee ,  Sung-min Cho ,  Sae-hoon Chung

Inventor： Geun-young Yeom ,  Min-jae Chung ,  Do-haing Lee ,  Sung-min Cho ,  Sae-hoon Chung

IPC: H01L21/3065 ,  C23F4/00 ,  C23C16/00 ,  C23F1/00

CPC classification number: C23F4/00 ,  H01J2237/08

Abstract: A layer-by-layer etching apparatus and an etching method using a neutral beam which enables to control etching depth to an atomic level by controlling the etching of each atom of a material layer to be etched under precise control of the supply of an etching gas and irradiation of the neutral beam and enables to minimize etching damage. In the layer-by-layer etching method, a substrate to be etched, on which a layer to be etched is exposed, is loaded on a stage in a reaction chamber. An etching gas is supplied into the reaction chamber to adsorb the etching gas on the surface of an exposed portion of the layer to be etched. Excessive etching gas remaining after being adsorbed is removed. A neutral beam is irradiated on the layer to be etched on which the etching gas is adsorbed. Etch by-products generated by the irradiation of the neutral beam is removed.

Abstract translation: 一种逐层蚀刻装置和使用中性光束的蚀刻方法，其能够通过在精确控制蚀刻气体的供给的精确控制下控制蚀刻材料层的每个原子的蚀刻，从而将蚀刻深度控制为原子水平 并照射中性光束并且能够最小化蚀刻损伤。 在逐层蚀刻方法中，将要蚀刻的层被蚀刻的基板暴露在反应室的台上。 将蚀刻气体供应到反应室中，以将蚀刻气体吸附在被蚀刻层的暴露部分的表面上。 吸附后残留的蚀刻气体过剩被去除。 中性光束照射在被蚀刻的蚀刻气体被吸附的层上。 除去由中性束的照射产生的副产物。

公开(公告)号：US08900944B2

公开(公告)日：2014-12-02

申请号：US13307270

申请日：2011-11-30

Applicant: Soo-Yeon Jeong ,  Myeong-Cheol Kim ,  Do-Hyoung Kim ,  Do-Haing Lee ,  Nam-Myun Cho ,  In-Ho Kim

Inventor： Soo-Yeon Jeong ,  Myeong-Cheol Kim ,  Do-Hyoung Kim ,  Do-Haing Lee ,  Nam-Myun Cho ,  In-Ho Kim

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L27/088 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device includes forming a gate structure through a first insulating interlayer on a substrate such that the gate structure includes a spacer on a sidewall thereof, forming a first hard mask on the gate structure, partially removing the first insulating interlayer using the first hard mask as an etching mask to form a first contact hole such that the first contact hole exposes a top surface of the substrate, forming a metal silicide pattern on the top surface of the substrate exposed by the first contact hole, and forming a plug electrically connected to the metal silicide pattern.

Abstract translation: 一种制造半导体器件的方法包括通过基板上的第一绝缘中间层形成栅极结构，使得栅极结构在其侧壁上包括间隔物，在栅极结构上形成第一硬掩模，使用 所述第一硬掩模作为蚀刻掩模以形成第一接触孔，使得所述第一接触孔暴露所述基板的顶表面，在所述基板的由所述第一接触孔暴露的所述顶表面上形成金属硅化物图案，并形成 插头电连接到金属硅化物图案。

公开(公告)号：US08318412B2

公开(公告)日：2012-11-27

申请号：US12871251

申请日：2010-08-30

Applicant: Tokashiki Ken ,  Chul-ho Shin ,  Sang-Kuk Kim ,  Do-haing Lee ,  Dong-seok Lee

Inventor： Tokashiki Ken ,  Chul-ho Shin ,  Sang-Kuk Kim ,  Do-haing Lee ,  Dong-seok Lee

IPC: G03F7/26

CPC classification number: H01L21/31138 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/10855

Abstract: A semiconductor device is manufactured by a method including processes of trimming and molding resist patterns. A resist layer formed on a substrate is exposed and developed to form the resist patterns. The resist patterns are trimmed using a first gas plasma to change the profiles of the resist patterns. Widths of the trimmed resist patterns are increased using a second gas plasma to form processed resist patterns.

Abstract translation: 通过包括修整和成型抗蚀剂图案的工艺的方法制造半导体器件。 形成在基板上的抗蚀剂层被曝光和显影以形成抗蚀剂图案。 使用第一气体等离子体来修整抗蚀剂图案以改变抗蚀剂图案的轮廓。 使用第二气体等离子体增加修整的抗蚀剂图案的宽度以形成经处理的抗蚀剂图案。

公开(公告)号：US20120156867A1

公开(公告)日：2012-06-21

申请号：US13307270

申请日：2011-11-30

Applicant: Soo-Yeon Jeong ,  Myeong-Cheol Kim ,  Do-Hyoung Kim ,  Do-Haing Lee ,  Nam-Myun Cho ,  In-Ho Kim

Inventor： Soo-Yeon Jeong ,  Myeong-Cheol Kim ,  Do-Hyoung Kim ,  Do-Haing Lee ,  Nam-Myun Cho ,  In-Ho Kim

IPC: H01L21/283

CPC classification number: H01L27/088 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device includes forming a gate structure through a first insulating interlayer on a substrate such that the gate structure includes a spacer on a sidewall thereof, forming a first hard mask on the gate structure, partially removing the first insulating interlayer using the first hard mask as an etching mask to form a first contact hole such that the first contact hole exposes a top surface of the substrate, forming a metal silicide pattern on the top surface of the substrate exposed by the first contact hole, and forming a plug electrically connected to the metal silicide pattern.

Abstract translation: 一种制造半导体器件的方法包括通过基板上的第一绝缘中间层形成栅极结构，使得栅极结构在其侧壁上包括间隔物，在栅极结构上形成第一硬掩模，使用 所述第一硬掩模作为蚀刻掩模以形成第一接触孔，使得所述第一接触孔暴露所述基板的顶表面，在所述基板的由所述第一接触孔暴露的所述顶表面上形成金属硅化物图案，并形成 插头电连接到金属硅化物图案。