公开(公告)号：US06753218B2

公开(公告)日：2004-06-22

申请号：US10375303

申请日：2003-02-27

Applicant: Daniel Devoe ,  Alan Devoe ,  Lambert Devoe ,  Hung Trinh

Inventor： Daniel Devoe ,  Alan Devoe ,  Lambert Devoe ,  Hung Trinh

IPC: H01L218242

CPC classification number: H01G4/232 ,  H01G4/228 ,  H01L2224/48091 ,  H01L2924/19107 ,  H05K1/0306 ,  H05K1/162 ,  H01L2924/00014

Abstract: A capacitor including at least one interior metallization plane or plate and a multiplicity of vias for forming multiple redundant electrical connections within the capacitor. Series capacitors are provided having at least two interior plates redundantly electrically connected to at least two respective exterior plates. R-C devices are provided having multiple redundant vias filled with resistor material and/or conductor material to provide a resistor either in series with or parallel to a capacitor. Capacitors and R-C devices are provided having end terminations for applying voltage differential. Further, a method for making single capacitors, multiple parallel array capacitors, series capacitors and R-C devices is provided in which the chips are formed from the bottom up.

Abstract translation: 包括至少一个内部金属化平面或板的电容器和用于在电容器内形成多个冗余电连接的多个通孔。 提供串联电容器，其具有冗余地电连接到至少两个相应外部板的至少两个内部板。 R-C器件具有多个填充有电阻材料和/或导体材料的冗余通孔，以提供与电容器串联或并联的电阻器。 提供电容器和R-C器件，其具有用于施加电压差的终端。 此外，提供了用于制造单个电容器，多个并联阵列电容器，串联电容器和R-C器件的方法，其中芯片从下向上形成。

公开(公告)号：US20080291602A1

公开(公告)日：2008-11-27

申请号：US11753090

申请日：2007-05-24

Applicant: Daniel Devoe

Inventor： Daniel Devoe

IPC: H01G4/232 ,  B23P19/00

CPC classification number: H01G4/232 ,  H01G4/38 ,  H01G13/006 ,  H05K1/0203 ,  H05K3/3426 ,  H05K3/3447 ,  H05K2201/10469 ,  H05K2201/10537 ,  H05K2201/10636 ,  H05K2201/10659 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/53174

Abstract: A capacitor device, which is mountable on a substrate, has an electrically conductive bottom lead frame with a bottom plate mountable substantially parallel to, and in contact with, the substrate and an electrically conductive top lead frame having a top plate spaced apart from the bottom plate and a first transition portion having a first end connected to the top plate and a second end, opposite the first end, electrically connectable to the substrate. Multilayer capacitors are mounted between the top plate and the bottom plate. The capacitors have opposed end terminations electrically connected to the top and bottom plates, such that internal electrode plates are substantially nonparallel to the substrate.

Abstract translation: 可安装在基板上的电容器装置具有导电底部引线框架，其具有可安装为基本上平行于基板并与其接触的底板，以及导电顶部引线框架，其具有与底部间隔开的顶板 板和第一过渡部分，其具有连接到顶板的第一端和与第一端相对的第二端，其可电连接到基板。 多层电容器安装在顶板和底板之间。 电容器具有电连接到顶板和底板的相对端端，使得内部电极板基本上不平行于衬底。

公开(公告)号：US07307829B1

公开(公告)日：2007-12-11

申请号：US11249600

申请日：2005-10-13

Applicant: Daniel Devoe ,  Alan Devoe ,  Lambert Devoe

Inventor： Daniel Devoe ,  Alan Devoe ,  Lambert Devoe

IPC: H01G4/228 ,  H01G4/06

CPC classification number: H01G4/38 ,  H01G2/065 ,  H01G4/30 ,  H05K1/0231 ,  H05K2201/10522 ,  H05K2201/10689

Abstract: A monolithic capacitor structure includes opposed and overlapping plates within a dielectric body, which are arranged to form a lower frequency, higher value capacitor. Other conductive structure is located either inside the dielectric body or on an external surface thereof and is effective to form a higher frequency, lower value capacitor in parallel with the lower frequency, higher value capacitor. The resulting array of combined series and parallel capacitors integral with the dielectric body provides effective wideband performance in an integrated, cost-effective structure.

Abstract translation: 单片电容器结构包括介电体内的相对和重叠的板，它们被布置成形成较低频率的较高值的电容器。 其他导电结构位于电介质体内部或其外表面上，并且有效地与较低频率的较高值电容器并联形成较高频率的较低值电容器。 与电介质体集成的组合串联和并联电容器的阵列在集成的，具有成本效益的结构中提供了有效的宽带性能。

公开(公告)号：US07035080B1

公开(公告)日：2006-04-25

申请号：US10994866

申请日：2004-11-22

Applicant: Lambert Devoe ,  Alan Devoe ,  Daniel Devoe

Inventor： Lambert Devoe ,  Alan Devoe ,  Daniel Devoe

IPC: H01G4/228 ,  H01G4/005

CPC classification number: H01G4/232 ,  H01G2/06 ,  H01L2224/48464 ,  H01L2924/09701 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/0306 ,  H05K1/113 ,  H05K1/162 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09627 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K2203/049

Abstract: A substrate includes a single-layer capacitor and various external contacts. A first external contact provides a first electrical connection to the single-layer capacitor. A second external contact provides a second electrical connection to the single-layer capacitor. The first and third external contacts are electrically connectable to another electrical component, and internal metallization structures or vias of conductive material electrically connect the second contact and the third contact to facilitate the single-layer capacitor being connectable in a parallel circuit with the other electrical component.

Abstract translation: 衬底包括单层电容器和各种外部触点。 第一外部触点提供与单层电容器的第一电连接。 第二外部触点提供与单层电容器的第二电连接。 第一和第三外部触点可电连接到另一个电气部件，并且导电材料的内部金属化结构或通路电连接第二触点和第三触点，以便于单层电容器可以与并联电路与另一个电气部件 。

公开(公告)号：US06690558B1

公开(公告)日：2004-02-10

申请号：US10047588

申请日：2002-01-14

Applicant: Alan Devoe ,  Daniel Devoe

Inventor： Alan Devoe ,  Daniel Devoe

IPC: H02H900

CPC classification number: H01C1/148 ,  H01C7/18 ,  H01C17/006 ,  H01C17/28

Abstract: A high power resistor device and method for making a high power resistor device. A resistor is formed on a first end of a fired, ceramic chip with multiple internal conductor electrodes, and end terminations are then applied to both ends of the chip. A power resistor device having a high power rating is thus provided having buried conductor electrodes electrically connected to end terminations, where the connection at the first end is through the resistor to form a power resistor structured to dissipate heat efficiently. In an alternative method of the present invention, both ends of the chip may be dipped in resistor paste to form resistors on both ends of the chip. In yet another alternative method of the present invention, a conductor under-layer is formed under the resistor, such as by first dipping the end of the chip in a conductor paste and firing the chip.

Abstract translation: 一种用于制造高功率电阻器件的高功率电阻器件和方法。 在具有多个内部导体电极的烧制陶瓷芯片的第一端上形成电阻器，然后将端接端子施加到芯片的两端。 因此，提供具有高功率额定值的功率电阻器件，其具有电连接到端部端子的掩埋导体电极，其中第一端处的连接通过电阻器以形成有效地散热的功率电阻器。 在本发明的替代方法中，芯片的两端可以浸入电阻浆料中以在芯片的两端形成电阻器。 在本发明的另一种替代方法中，在电阻器的下方形成导体底层，例如首先将芯片的端部浸入导体糊料中并烧制芯片。

公开(公告)号：US06587327B1

公开(公告)日：2003-07-01

申请号：US10150202

申请日：2002-05-17

Applicant: Daniel Devoe ,  Alan Devoe ,  Lambert Devoe

Inventor： Daniel Devoe ,  Alan Devoe ,  Lambert Devoe

IPC: H01G4228

CPC classification number: H01G4/30 ,  H01G4/228 ,  H01G4/38

Abstract: A monolithic capacitor structure includes at least first and second plates internal to a dielectric body, the plates extending inward from opposed conductive contacts on surfaces of the body, and forming capacitor(s) therebetween. A third plate extends within said body, electrically floating relative to the exterior contacts, and forming a capacitor with the first and second plates, and further forming a capacitor with additional conductive structures connected to the conductive contacts on the body. The resulting array of combined series and parallel capacitors formed by the third plate, in conjunction with the capacitor(s) formed by the first and second plates, provides effective wideband performance in an integrated, cost-effective structure.

Abstract translation: 单片电容器结构至少包括介电体内部的第一和第二板，所述板从主体表面上的相对的导电触点向内延伸，并且在它们之间形成电容器。 第三板在所述主体内延伸，相对于外部触头电浮动，以及与第一和第二板形成电容器，并进一步形成具有连接到主体上的导电触点的附加导电结构的电容器。 由第三板形成的所组合的串联和并联电容器阵列与由第一和第二板形成的电容器相结合，在集成的，具有成本效益的结构中提供了有效的宽带性能。

公开(公告)号：US6081416A

公开(公告)日：2000-06-27

申请号：US87209

申请日：1998-05-28

Applicant: Hung Trinh ,  Alan D. Devoe ,  Daniel Devoe

Inventor： Hung Trinh ,  Alan D. Devoe ,  Daniel Devoe

IPC: H01G4/12 ,  H01G4/228 ,  H01G4/232 ,  H05K3/34 ,  H01G2/20

CPC classification number: H01G4/2325 ,  H01G4/12 ,  H01G4/228 ,  H01G4/232 ,  H05K3/3426

Abstract: A ceramic electrical device or component, normally a barium titanate ceramic capacitor, having a first coefficient of thermal expansion (CTE), typically about 10 parts per million per degree centigrade (10 ppm/.degree.C.), is physically and electrically mounted through an intermediary solder layer, normally copper, to a lead frame, normally made from a selected alloy of nickel-iron, having a second CTE at least one-fifth (20%) less, and more typically about 5 ppm/.degree.C., or one-half (50%) less, than is the CTE of the ceramic capacitor. Because ceramics are stronger in compression than in tension, the ceramic capacitor held within the lead frame is less likely to undergo a stress fracture at temperatures elevated above those of assembly than would be the case should the CTE's be equal, or should the CTE of the lead frame be greater than the CTE of the ceramic capacitor. Leaded ceramic capacitors, stacked multilayer ceramic capacitors, ceramic inductors and ceramic resistors so constructed satisfy United States standards for electronic components used in broad-temperature-range demanding military and space applications.

Abstract translation: 通常具有第一热膨胀系数（CTE）的陶瓷电气装置或部件，通常为钛酸钡陶瓷电容器，通常约为10ppm /摄氏度（10ppm /℃），通过以下方式物理和电气安装： 中间焊料层，通常为铜，通常由选择的镍 - 铁合金制成，具有第二CTE至少五分之一（20％），更通常约5ppm /℃的引线框，或 比陶瓷电容器的CTE少一半（50％）。 由于陶瓷的压缩强度比拉伸强度高，所以保持在引线框架内的陶瓷电容器在高于组装温度的温度下不太可能发生应力断裂，而不是CTE等于或者CTE 引线框架大于陶瓷电容器的CTE。 有铅陶瓷电容器，堆叠多层陶瓷电容器，陶瓷电感器和陶瓷电阻器的结构符合美国在宽温度要求苛刻的军事和空间应用中使用的电子元件的标准。