公开(公告)号：US08809687B2

公开(公告)日：2014-08-19

申请号：US13077304

申请日：2011-03-31

Applicant: Hirohito Watanabe

Inventor： Hirohito Watanabe

IPC: H05K1/00 ,  H05K1/03 ,  H05K9/00

CPC classification number: H05K1/028 ,  H05K1/0218 ,  H05K3/1216 ,  H05K2201/0373

Abstract: [Object]To provide a flexible printed board improved in bendability.[Means for solving]The flexible printed board 2 comprises: an insulating substrate 21; a circuit wiring 22 laid on the insulating substrate 21; a circuit protection layer 23 laid on the circuit wiring 22; a shield conductive layer 24 laid on the circuit protection layer 23; and a shield insulating layer 25 laid on the shield conductive layer 24, and is characterized by meeting the following Expression (1). 0.75≦E2/E1≦1.29  Expression (1) Note that E1 denotes the tensile elastic modulus of the shield conductive layer 24 and E2 denotes the tensile elastic modulus of the shield insulating layer 25.

Abstract translation: 提供改善弯曲性的柔性印刷电路板。 [解决方案]柔性印刷电路板2包括：绝缘基板21; 布置在绝缘基板21上的电路布线22; 布置在电路布线22上的电路保护层23; 布置在电路保护层23上的屏蔽导电层24; 以及敷设在屏蔽导电层24上的屏蔽绝缘层25，其特征在于满足下述式（1）。 0.75＆nlE; E2 / E1＆nlE; 1.29表达式（1）注意，E1表示屏蔽导电层24的拉伸弹性模量，E2表示屏蔽绝缘层25的拉伸弹性模量。

公开(公告)号：US08574449B2

公开(公告)日：2013-11-05

申请号：US13462399

申请日：2012-05-02

Applicant: Hirohito Watanabe ,  Taiji Ogawa ,  Eriko Tomonaga

Inventor： Hirohito Watanabe ,  Taiji Ogawa ,  Takaomi Tomonaga

IPC: B44C1/22

CPC classification number: H05K1/0269 ,  H05K3/06 ,  H05K2201/09781 ,  H05K2203/1545 ,  H05K2203/163

Abstract: Quickly making changes to etching conditions suppresses the production yield of printed wiring boards from being deteriorated. Disclosed is a method comprising: an etching step that comprises: preparing a conductor-clad base material continuous in a certain direction, the conductor-clad base material (1) having an insulating layer and one or more conductive layers formed on main surfaces of the insulating layer; and subjecting a predetermined region of a conductor layer of one main surface of the conductor-clad base material (1) to an etching process thereby to form a wiring pattern (1a) to be of a product and an inspection pattern (1b) to be used for inspection; a measuring step that measures a line width of the inspection pattern after the etching step; and a control step that controls an etching condition in the etching step based on the measured line width.

Abstract translation: 迅速改变蚀刻条件抑制了印刷电路板的生产成本的恶化。 公开了一种方法，包括：蚀刻步骤，包括：制备在一定方向上连续的导体包覆基材，所述导体包覆基材（1）具有绝缘层和形成在所述导体包覆基材的主表面上的一个或多个导电层 绝缘层; 并且对导体包覆基材（1）的一个主表面的导体层的预定区域进行蚀刻处理，从而形成作为产品的布线图案（1a）和检查图案（1b） 用于检验; 测量步骤，其测量所述蚀刻步骤之后的所述检查图案的线宽; 以及控制步骤，其基于所测量的线宽来控制蚀刻步骤中的蚀刻条件。

公开(公告)号：US07759744B2

公开(公告)日：2010-07-20

申请号：US11129440

申请日：2005-05-16

Applicant: Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

Inventor： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/62 ,  H01L27/10 ,  H01L29/73

CPC classification number: H01L29/517 ,  H01L21/823857 ,  H01L29/4916 ,  H01L29/513 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device 100 includes a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 12 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from Hf and Zr.

Abstract translation: 半导体器件100包括硅衬底102，在硅衬底102上包括第一高介电常数膜111和多晶硅膜114的N型MOSFET 118和包括第二高介电常数膜的P型MOSFET 120 12和与硅衬底102上的N型MOSFET 118并列的多晶硅膜114.第二高介电常数膜112形成为具有比第一高介电常数膜111的膜厚薄的膜厚度。第一 高介电常数膜111和第二高介电常数膜112含有选自Hf和Zr的一种或多种元素。

公开(公告)号：US06804442B1

公开(公告)日：2004-10-12

申请号：US10449192

申请日：2003-06-02

Applicant: Hirohito Watanabe ,  Keiji Ohashi

Inventor： Hirohito Watanabe ,  Keiji Ohashi

IPC: G02B602

CPC classification number: G02B6/4403 ,  G02B6/02395

Abstract: An improved optical fiber is described. The optical fiber comprises: a fiber glass structure; a first jacket layer made of a soft curable resin and directly covering the external surface of said fiber glass structure; and a second jacket layer made of a rigid curable resin and covering the external surface of said fiber glass structure through said first jacket layer. The mechanical factors of said fiber glass structure, the mechanical factors of said first jacket layer and the mechanical factors of said second jacket layer are selected in order that the Young's modulus of said first jacket layer is larger than the average tensile stress (&sgr;r+&sgr;&thgr;+&sgr;z)/3 as applied to said first jacket layer 5 while the resin temperature of UV curable resins largely falls from the temperature when the rigid UV curable resin starts hardening to the temperature when the hardening is finished.

Abstract translation: 描述了改进的光纤。 光纤包括：玻璃纤维结构; 由软固化树脂制成的第一护套层，并直接覆盖所述玻璃纤维结构体的外表面; 以及由刚性可固化树脂制成的第二护套层，并通过所述第一护套层覆盖所述玻璃纤维结构的外表面。 选择所述玻璃纤维结构的机械因素，所述第一护套层的机械因素和所述第二护套层的机械因素，使得所述第一护套层的杨氏模量大于平均拉伸应力（sigmar + sigmatheta + sigmaz）/ 3，而UV硬化树脂的树脂温度从刚性UV固化树脂开始硬化时的温度到硬化结束时的温度大大降低。

公开(公告)号：US6146966A

公开(公告)日：2000-11-14

申请号：US859210

申请日：1997-05-20

Applicant: Toshiyuki Hirota ,  Hirohito Watanabe ,  Fumiki Aiso ,  Shuji Fujiwara ,  Masanobu Zenke

Inventor： Toshiyuki Hirota ,  Hirohito Watanabe ,  Fumiki Aiso ,  Shuji Fujiwara ,  Masanobu Zenke

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L28/84 ,  H01L27/10852

Abstract: In a process of forming hemi-spherical silicon grains on an amorphous silicon film in accordance with the "crystal nucleation" process, in order to form crystal nuclei on a top surface and a side surface of the amorphous silicon film, SiH.sub.4 is irradiated onto the top and side surfaces of the amorphous silicon film at a stabilized temperature which is lower than, by at least 5.degree. C., an annealing temperature for growing the hemi-spherical silicon grains from the crystal nuclei, with the result that it is possible to suppress or retard the growth of the crystals growing into the amorphous silicon film from a boundary between the amorphous silicon film and an interlayer insulator film. Thereafter, the amorphous silicon film having the crystal nuclei thus formed on the surface thereof is annealed at the annealing temperature so that the hemi-spherical silicon grains are formed on the whole surface of the top and side surfaces of the amorphous silicon film.

Abstract translation: 在根据“晶体成核”法在非晶硅膜上形成半球形硅晶粒的过程中，为了在非晶硅膜的顶表面和侧表面上形成晶核，将SiH 4照射到 该非晶硅膜的顶表面和侧表面在稳定的温度下低于至少5℃的用于从晶核生长半球形硅晶粒的退火温度，结果是可以 从非晶硅膜和层间绝缘膜之间的边界抑制或延缓从非晶硅膜生长的晶体的生长。 此后，在其表面上形成具有晶核的非晶硅膜在退火温度下退火，使得半球形硅晶粒形成在非晶硅膜的顶表面和侧表面的整个表面上。

公开(公告)号：US5973355A

公开(公告)日：1999-10-26

申请号：US851285

申请日：1997-05-05

Applicant: Hiroki Shirai ,  Taishi Kubota ,  Ichiro Honma ,  Hirohito Watanabe ,  Haruhiko Ono ,  Takeshi Okazawa

Inventor： Hiroki Shirai ,  Taishi Kubota ,  Ichiro Honma ,  Hirohito Watanabe ,  Haruhiko Ono ,  Takeshi Okazawa

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7883 ,  Y10S257/90

Abstract: There is disclosed a nonvolatile semiconductor memory device, which is capable of maintaining a high capacitance ratio even when a memory cell is formed in a micronized size without increasing the number of manufacturing steps. In a flash memory having buried diffusion layer type cells, a source region and drain regions and are formed in self alignment with a polycrystalline film pattern which has a polycrystalline silicon film having projecting and recessing parts in its upper surface.

Abstract translation: 公开了一种非易失性半导体存储器件，即使在不增加制造步骤的数量的情况下，即使在微细尺寸形成存储单元时，也能够保持高电容比。 在具有掩埋扩散层型电池的闪速存储器中，源极区域和漏极区域形成为与其上表面具有突出和凹陷部分的多晶硅膜的多晶膜图案自对准地形成。

公开(公告)号：US5910019A

公开(公告)日：1999-06-08

申请号：US829358

申请日：1997-04-02

Applicant: Hirohito Watanabe ,  Ichiro Honma

Inventor： Hirohito Watanabe ,  Ichiro Honma

IPC: H01L21/285 ,  H01L21/02 ,  H01L21/205 ,  H01L21/28 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L27/11 ,  H01L21/00

CPC classification number: H01L27/10852 ,  H01L27/11 ,  H01L27/1108 ,  H01L28/84

Abstract: A method of forming a silicon layer disclosed herein includes the steps of depositing an amorphous silicon layer on a substrate, irradiating a silane gas to the substrate, and performing an annealing process in a high vacuum or in an inert gas. The amorphous silicon layer is thereby converted into a silicon layer having an uneven surface caused by hemispherical or spherical silicon grains. The annealing process may be performed while irradiating a hydrogen gas or an oxidizing gas. In this case, such a silicon layer that has an even surface is formed.

Abstract translation: 本文公开的形成硅层的方法包括以下步骤：在衬底上沉积非晶硅层，向衬底照射硅烷气体，并在高真空或惰性气体中进行退火处理。 从而将非晶硅层转变成由半球形或球形硅晶粒引起的具有不平坦表面的硅层。 可以在照射氢气或氧化气体的同时进行退火处理。 在这种情况下，形成具有均匀表面的硅层。

公开(公告)号：US5753949A

公开(公告)日：1998-05-19

申请号：US710939

申请日：1996-09-24

Applicant: Ichiroh Honma ,  Hirohito Watanabe

Inventor： Ichiroh Honma ,  Hirohito Watanabe

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: Used nearer to a MOS transistor (25, 29(1), 29(2)) together with another capacitor electrode (39) with a dielectric film (37) interposed for use in a DRAM, a capacitor electrode comprises a conductor pole (53) and a conductor layer (55) which is held by the conductor pole and comprises a plate portion (57) extended perpendicular to a pole axis and having a plate periphery and a peripheral portion (59) extended parallel to the pole axis from the plate periphery towards a pole end. Preferably, the conductor layer is held by the pole on a plurality of levels. A planar conductor layer may additionally be held at the pole end perpendicular to the pole axis. Word (41) and bit (49) lines are embedded in an insulator layer (43, 51) for the capacitor and the transistor.

Abstract translation: 与另一个电容器电极（39）一起更靠近MOS晶体管（25,29（1），29（2）），电容器电极插入用于DRAM中，电容器电极包括导体极（53 ）和导体层（55），所述导体层（55）由所述导体极保持，并且包括垂直于极轴延伸并具有板周边的平板部（57）和从所述平板平行于所述极轴延伸的周边部（59） 周边朝极端。 优选地，导体层由极保持在多个层上。 平面导体层可以另外保持在垂直于极轴的极端。 字（41）和位（49）线被嵌入用于电容器和晶体管的绝缘体层（43,41）中。

公开(公告)号：US5691249A

公开(公告)日：1997-11-25

申请号：US447561

申请日：1995-05-23

Applicant: Hirohito Watanabe ,  Toru Tatsumi

Inventor： Hirohito Watanabe ,  Toru Tatsumi

IPC: H01L21/02 ,  H01L27/108 ,  H01L21/205

CPC classification number: H01L28/84 ,  H01L27/10817 ,  H01L28/82 ,  H01L28/90 ,  Y10S438/964

Abstract: A method for fabricating a polycrystalline silicon having a roughed surface, which is useful for a capacitor electrode is disclosed. The method is featured by depositing a polycrystalline silicon layer in such a manner that grains of silicon are caused at the surface of the polycrystalline silicon layer. The polycrystalline silicon layer thus obtained has a large effective surface area and is suitable for a capacitor electrode because of its increased effective surface area.

Abstract translation: 公开了一种用于制造具有粗糙表面的多晶硅的方法，其用于电容器电极。 该方法的特征在于以如下方式沉积多晶硅层，即在多晶硅层的表面引起硅晶粒。 这样获得的多晶硅层具有大的有效表面积，由于其有效表面积增加，因此适用于电容器电极。

公开(公告)号：US5397748A

公开(公告)日：1995-03-14

申请号：US996978

申请日：1992-12-24

Applicant: Hirohito Watanabe ,  Sadayuki Ohnishi

Inventor： Hirohito Watanabe ,  Sadayuki Ohnishi

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/321

CPC classification number: H01L28/40 ,  H01L21/3145 ,  H01L21/32105 ,  H01L21/3211 ,  Y10S148/014

Abstract: A thermal oxidation method for producing a semiconductor device having a capacitor insulating film structure capable of making a thin film having a small leakage current and small temperature dependence of the leakage current. In the insulating film, a silicon nitride film with a small electron mobility and a silicon oxide film with a small hole mobility are alternately laminated in order of the nitride film/oxide film/nitride film/oxide film from a lower electrode side. A current component such as electrons flowing in this insulating film structure is limited by the layer with the smaller mobility to reduce the leakage current. An oxide film thickness of approximately several .ANG. can thus be strictly controlled. By forming the silicon nitride film between the high dielectric oxide film and the electrode, the reaction of the silicon electrode and the high dielectric oxide film can be prevented.

Abstract translation: 一种用于制造具有能够制造具有小泄漏电流和较小的漏电流的温度依赖性的薄膜的电容器绝缘膜结构的半导体器件的热氧化方法。 在绝缘膜中，具有小电子迁移率的氮化硅膜和具有小空穴迁移率的氧化硅膜按照来自下电极侧的氮化物膜/氧化膜/氮化物膜/氧化物膜的顺序交替层叠。 在该绝缘膜结构中流动的电子的电流成分被具有较小迁移率的层限制，以减少漏电流。 因此可以严格控制大约几个ANGSTROM的氧化膜厚度。 通过在高电介质氧化膜和电极之间形成氮化硅膜，可以防止硅电极和高电介质氧化膜的反应。