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    Wire bonding method and apparatus for electromagnetic interference shielding
    12.
    发明授权
    Wire bonding method and apparatus for electromagnetic interference shielding 有权

    公开(公告)号：US10658302B2

    公开(公告)日：2020-05-19

    申请号：US15914617

    申请日：2018-03-07

    Applicant: Invensas Corporation

    Inventor： Shaowu Huang ,  Javier A. Delacruz

    IPC: H01L23/552 ,  H01L23/31 ,  H01L21/56

    Abstract: Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.

    Structures And Methods For Low Temperature Bonding Using Nanoparticles
    13.
    发明申请
    Structures And Methods For Low Temperature Bonding Using Nanoparticles 审中-公开

    公开(公告)号：US20200152598A1

    公开(公告)日：2020-05-14

    申请号：US16740670

    申请日：2020-01-13

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh

    IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

    Abstract: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

    Multi-chip modules formed using wafer-level processing of a reconstituted wafer
    15.
    发明授权
    Multi-chip modules formed using wafer-level processing of a reconstituted wafer 有权

    公开(公告)号：US10546834B2

    公开(公告)日：2020-01-28

    申请号：US16246863

    申请日：2019-01-14

    Applicant: Invensas Corporation

    Inventor： Liang Wang ,  Rajesh Katkar

    IPC: H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00

    Abstract: Apparatuses and methods are described. This apparatus includes a bridge die having first contacts on a die surface being in a molding layer of a reconstituted wafer. The reconstituted wafer has a wafer surface including a layer surface of the molding layer and the die surface. A redistribution layer on the wafer surface includes electrically conductive and dielectric layers to provide conductive routing and conductors. The conductors extend away from the die surface and are respectively coupled to the first contacts at bottom ends thereof. At least second and third IC dies respectively having second contacts on corresponding die surfaces thereof are interconnected to the bridge die and the redistribution layer. A first portion of the second contacts are interconnected to top ends of the conductors opposite the bottom ends thereof in part for alignment of the at least second and third IC dies to the bridge die.

    Method and apparatus for stacking devices in an integrated circuit assembly
    16.
    发明授权
    Method and apparatus for stacking devices in an integrated circuit assembly 有权

    公开(公告)号：US10515838B2

    公开(公告)日：2019-12-24

    申请号：US16193679

    申请日：2018-11-16

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh

    IPC: H01L21/76 ,  H01L21/683 ,  H01L25/00 ,  H01L23/00 ,  H01L21/67 ,  H01L25/065

    Abstract: Methods and apparatuses for stacking devices in an integrated circuit assembly are provided. A tray for supporting multiple dies of a semiconductor material enables both top side processing and bottom side processing of the dies. The dies can be picked and placed for bonding on a substrate or on die stacks without flipping the dies, thereby avoiding particulate debris from the diced edges of the dies from interfering and contaminating the bonding process. In an implementation, a liftoff apparatus directs a pneumatic flow of gas to lift the dies from the tray for bonding to a substrate, and to previously bonded dies, without flipping the dies. An example system allows processing of both top and bottom surfaces of the dies in a single cycle in preparation for bonding, and then pneumatically lifts the dies up to a target substrate so that top sides of the dies bond to bottom sides of dies of the previous batch, in an efficient and flip-free assembly of die stacks.

    HIGH YIELD SUBSTRATE ASSEMBLY
    18.
    发明申请
    HIGH YIELD SUBSTRATE ASSEMBLY 审中-公开

    公开(公告)号：US20190341361A1

    公开(公告)日：2019-11-07

    申请号：US16514104

    申请日：2019-07-17

    Applicant: Invensas Corporation

    Inventor： Liang Wang ,  Ilyas Mohammed ,  Masud Beroz

    IPC: H01L23/00 ,  H01L21/02 ,  H01L21/683 ,  H01L23/544 ,  H01L25/00 ,  H01L33/00 ,  H01L27/02

    Abstract: High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.

    MULTI-DIE MODULE WITH LOW POWER OPERATION
    19.
    发明申请
    MULTI-DIE MODULE WITH LOW POWER OPERATION 审中-公开

    公开(公告)号：US20190333550A1

    公开(公告)日：2019-10-31

    申请号：US16397569

    申请日：2019-04-29

    Applicant: Invensas Corporation

    Inventor： David Edward Fisch

    IPC: G11C5/14 ,  H01L25/065 ,  H01L27/108 ,  G11C7/10 ,  G11C5/04 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/406

    Abstract: A module for multiple dies is disclosed. The module can include a group of dies that include a first die having a first voltage block and a second die having a second voltage block. The module can also include an interconnect that electrically connects the first and second dies. Power supply generation in the first die is enabled in non-active mode, while power supply generation in the second die is disabled. The power supply generation in the second die may be enabled when the second die is in active mode. The first die can send enabling signal to the second the die to enable the second die. The first die can provide supply to the second die in the non-active mode. The first die can send self-refresh timing command to the second die when the module is in a self-refresh mode.

    Embedded organic interposers for high bandwidth
    20.
    发明授权
    Embedded organic interposers for high bandwidth 有权

    公开(公告)号：US10403599B2

    公开(公告)日：2019-09-03

    申请号：US15499557

    申请日：2017-04-27

    Applicant: Invensas Corporation

    Inventor： Javier A. Delacruz ,  Belgacem Haba

    IPC: H01L25/16 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498

    Abstract: Embedded organic interposers for high bandwidth are provided. Example embedded organic interposers provide thick conductors with more dielectric space, and more routing layers of such conductors than conventional interposers, in order to provide high bandwidth transmission capacity over longer spans. The embedded organic interposers provide high bandwidth transmission paths between components such as HBM, HBM2, and HBM3 memory stacks, and other components. To provide the thick conductors and more routing layers for greater transmission capacity, extra space is achieved by embedding the organic interposers in the core of the package. Example embedded organic interposers lower a resistive-capacitive (RC) load of the routing layers to provide improved signal transmission of 1-2 GHz up to 20-60 GHz bandwidth for each 15 mm length, for example. The embedded organic interposers are not limited to use with memory modules.

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