公开(公告)号：US08780420B1

公开(公告)日：2014-07-15

申请号：US13838245

申请日：2013-03-15

Applicant: Nathan Bluzer ,  James Halvis

Inventor： Nathan Bluzer ,  James Halvis

IPC: H04N1/04 ,  G06K9/46 ,  G06K9/40

CPC classification number: H04N1/04

Abstract: A focal plane staring sensor is provided that includes an M×N sensor, where M is a number of rows of sensor pixels in the sensor and N is a number of columns of sensor pixels in the sensor, where M and N are integers greater than one. A control circuit samples a sensor pixel value for each sensor pixel of the M×N sensor at a plurality of different integration times corresponding to an amount of time that a photonic charge can be acquired in each sensor pixel of the M×N sensor, wherein the control circuit selects one sample from a set of samples to generate a scaled value to facilitate an equalization of a signal to noise ratio between the sensor pixels.

Abstract translation: 提供了一种焦平面凝视传感器，其包括M×N传感器，其中M是传感器中的传感器像素的行数，N是传感器中的传感器像素列数，其中M和N是大于 一。 控制电路以对应于在M×N传感器的每个传感器像素中可获取光子电荷的时间量的多个不同积分时间，对M×N传感器的每个传感器像素的传感器像素值进行采样，其中 控制电路从一组样本中选择一个采样以产生一个缩放的值，以促进传感器像素之间的信噪比的均衡。

公开(公告)号：US07468504B2

公开(公告)日：2008-12-23

申请号：US11370846

申请日：2006-03-09

Applicant: James Halvis ,  Richard Calve McKee

Inventor： James Halvis ,  Richard Calve McKee

IPC: G01J3/50 ,  H01J5/16 ,  H01J40/14

CPC classification number: G01J3/2823 ,  G01J3/021 ,  G01J3/08 ,  G01J3/36 ,  G01J2003/2826

Abstract: The present invention provides a spectral filter for an optical sensor. The spectral filter includes a substrate having a focus region and a defocus region, a panchromatic filter region disposed on the focus region of the substrate and a multi-spectral filter region disposed on the defocus region of the substrate. The panchromatic filter region includes a plurality of panchromatic pixels, while the multi-spectral filter region includes a plurality of multi-spectral pixels. Each of the multi-spectral pixels includes a plurality of color pixels.

Abstract translation: 本发明提供一种用于光学传感器的光谱滤波器。 光谱滤光器包括具有聚焦区域和散焦区域的基板，设置在基板的焦点区域上的全色滤光器区域和设置在基板的散焦区域上的多光谱滤光器区域。 全色滤波器区域包括多个全色像素，而多光谱滤波器区域包括多个多光谱像素。 每个多光谱像素包括多个彩色像素。

公开(公告)号：US5606187A

公开(公告)日：1997-02-25

申请号：US491666

申请日：1995-06-19

Applicant: Nathan Bluzer ,  James Halvis

Inventor： Nathan Bluzer ,  James Halvis

IPC: H01L27/148

CPC classification number: H01L27/148

Abstract: A CCD structure including high resolution pixels. The gate electrodes of the CCD are separated by gaps in the order of 0.6 .mu.m which are made to look smaller than their physical size by the use of dielectric filler material in the gaps. The dielectric filler material has a relatively high dielectric constant which is relatively large for the clock frequencies utilized but may be relatively low for optical frequencies. The dielectric constant of the dielectric filler material is typically greater than 20 and is selected from materials such as tantalum oxide, zirconium oxide, barium titanate and barium strontium titanate.

Abstract translation: 包括高分辨率像素的CCD结构。 通过在间隙中使用介质填充材料，将CCD的栅电极分开，间隙为0.6μm，通过使用介电填料材料制成的看起来比其物理尺寸小。 介电填料材料具有相对较高的介电常数，对于所使用的时钟频率而言相对较大，但对于光频率可能相对较低。 介电填充材料的介电常数通常大于20，并且选自氧化钽，氧化锆，钛酸钡和钛酸锶钡等材料。

公开(公告)号：US5120960A

公开(公告)日：1992-06-09

申请号：US691187

申请日：1991-04-25

Applicant: James Halvis

Inventor： James Halvis

IPC: H01L27/146 ,  H01L31/108

CPC classification number: H01L31/108 ,  H01L27/14649 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2924/12032

Abstract: An infrared (IR) imaging device includes substantially identical top and bottom IR detector arrays. In separate embodiments, either a top or bottom surface of the top array is stacked onto the bottom array to confront a top surface of the bottom array and so that individual detector elements and subarrays of the top array are aligned with corresponding detector elements and subarrays of the bottom array. The image readout circuits of both the top and bottom array are connected by wire bonding to readout control circuits formed in the peripheral region of the wafer in which the bottom array is formed.

Abstract translation: 红外（IR）成像装置包括基本相同的顶部和底部IR检测器阵列。 在单独的实施例中，顶部阵列的顶部或底部表面被堆叠到底部阵列上以面对底部阵列的顶部表面，并且使得顶部阵列的各个检测器元件和子阵列与对应的检测器元件和子阵列对准 底部阵列。 顶部和底部阵列的图像读出电路通过引线键合连接到形成在其中形成底部阵列的晶片的周边区域中的读出控制电路。

公开(公告)号：US4900688A

公开(公告)日：1990-02-13

申请号：US332856

申请日：1989-04-03

Applicant: James Halvis

Inventor： James Halvis

IPC: H01L21/339

CPC classification number: H01L29/66954

Abstract: A pseudo uniphase CCD array having four functional regions, a clocked barrier region, a clocked well region, a virtual barrier region, and a gate variable potential well region per stage. The described structure allows flexibility in setting operating voltages and avoids the breakdown and fabrication difficulties of a virtual well region. The device employs a virtual barrier plus adjacent MOS well fixed potential region and uses clocking of barrier and well regions to achieve charge transfer. A fabrication sequence and operating potential selection criteria are also included.

Abstract translation: 具有四个功能区域，时钟屏障区域，时钟阱区域，虚拟屏障区域和每级的栅极可变势阱区域的伪单相CCD阵列。 所描述的结构允许设置工作电压的灵活性并且避免虚拟阱区域的击穿和制造困难。 该器件采用虚拟屏障加上相邻的MOS固定电位区域，并使用势垒和阱区域的时钟来实现电荷转移。 还包括制造顺序和操作电位选择标准。

公开(公告)号：US4652339A

公开(公告)日：1987-03-24

申请号：US831908

申请日：1986-02-24

Applicant: Nathan Bluzer ,  James Halvis

Inventor： Nathan Bluzer ,  James Halvis

IPC: H01L21/339 ,  H01L21/306 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC classification number: H01L29/66954 ,  Y10S438/978

Abstract: A CCD gate definition process utilizing a thin film layer in a double masking process to form a first and second oxide layer over the polysilicon gate material to provide a profiled and tapered oxide layer over the gate without any re-entrant oxide steps.

Abstract translation: 在双掩模工艺中利用薄膜层的CCD栅极定义方法，以在多晶硅栅极材料上形成第一和第二氧化物层，以在栅极上提供异形和锥形的氧化物层，而不需要任何再循环的氧化物步骤。