公开(公告)号：US20120096414A1

公开(公告)日：2012-04-19

申请号：US13335785

申请日：2011-12-22

Applicant: Jason Sweis

Inventor： Jason Sweis

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F1/70

Abstract: Disclosed is a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement controlled breaks between features on the layout. The bridging features may also be used to facilitate or optimize multiple mask/exposure techniques that split a layout or features on a layout to address pitch problems.

Abstract translation: 公开了一种使用子分辨率辅助特征来实现受控断点的方法，系统和计算机程序产品。 添加子分辨率桥接功能以实现布局上的功能之间的受控中断。 桥接特征还可以用于促进或优化在布局上分割布局或特征以解决间距问题的多个掩模/曝光技术。

公开(公告)号：US08782586B2

公开(公告)日：2014-07-15

申请号：US12582366

申请日：2009-10-20

Applicant: Abdurrahman Sezginer ,  David Cooke Noice ,  Jason Sweis ,  Vassilios Gerousis ,  Sozen Yao

Inventor： Abdurrahman Sezginer ,  David Cooke Noice ,  Jason Sweis ,  Vassilios Gerousis ,  Sozen Yao

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

Abstract: Disclosed are a method, apparatus, and program product for routing an electronic design using double patterning that is correct by construction. The layout that has been routed will by construction be designed to allow successful manufacturing with double patterning, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with double patterning.

Abstract translation: 公开了一种使用通过构造正确的双重图案化来布线电子设计的方法，装置和程序产品。 已经布线的布局将通过结构设计，以允许双重图案化的成功制造，因为路由器将不允许布局中的路由配置不能用双重图案化成功制造。

公开(公告)号：US08438506B2

公开(公告)日：2013-05-07

申请号：US13335785

申请日：2011-12-22

Applicant: Jason Sweis

Inventor： Jason Sweis

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F1/70

Abstract: Disclosed is a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement controlled breaks between features on the layout. The bridging features may also be used to facilitate or optimize multiple mask/exposure techniques that split a layout or features on a layout to address pitch problems.

Abstract translation: 公开了一种使用子分辨率辅助特征来实现受控断点的方法，系统和计算机程序产品。 添加子分辨率桥接功能以实现布局上的功能之间的受控中断。 桥接特征还可以用于促进或优化在布局上分割布局或特征以解决间距问题的多个掩模/曝光技术。

公开(公告)号：US08103985B2

公开(公告)日：2012-01-24

申请号：US11934662

申请日：2007-11-02

Applicant: Jason Sweis

Inventor： Jason Sweis

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F1/70

Abstract: Disclosed is a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement controlled breaks between features on the layout. The bridging features may also be used to facilitate or optimize multiple mask/exposure techniques that split a layout or features on a layout to address pitch problems.

Abstract translation: 公开了一种使用子分辨率辅助特征来实现受控断点的方法，系统和计算机程序产品。 添加子分辨率桥接功能以实现布局上的功能之间的受控中断。 桥接特征还可以用于促进或优化在布局上分割布局或特征以解决间距问题的多个掩模/曝光技术。

公开(公告)号：US06888229B2

公开(公告)日：2005-05-03

申请号：US10872105

申请日：2004-06-18

Applicant: Thomas H. DiStefano ,  Gary W. Grube ,  Igor Y. Khandros ,  Gaetan Mathieu ,  Jason Sweis ,  Laurie Union ,  David Gibson

Inventor： Thomas H. DiStefano ,  Gary W. Grube ,  Igor Y. Khandros ,  Gaetan Mathieu ,  Jason Sweis ,  Laurie Union ,  David Gibson

IPC: H01L21/60 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H05K3/36 ,  H05K3/40

CPC classification number: H01L24/86 ,  H01L23/3107 ,  H01L23/49572 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49861 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H05K3/361 ,  H05K3/4084 ,  H01L2924/00

Abstract: A semiconductor chip mounting component includes a support structure adapted to engage a semiconductor chip. The support structure has a top surface, a bottom surface, and a gap extending through the support structure for defining first and second portions of the support structure on opposite sides of the gap. The support structure includes at least one elongated bus disposed alongside the gap, on the second portion of the support structure. The support structure includes a plurality of electrically conductive leads, each lead having a connection section extending across the gap, the connection section having a first end disposed on the first portion of the support structure, and a second end secured to the bus. Each lead includes a frangible section disposed between the first and second ends of the connection section, the frangible section having a cross-sectional area that is smaller than a cross-sectional area of the connection section. The gap is open at the bottom surface of the support structure. A semiconductor chip is disposed beneath the bottom surface of the support structure. The leads are adapted to be bonded to contacts on the semiconductor chip by breaking the frangible sections of the leads so as to disconnect the second ends of the leads from the bus and engage the leads with the contacts of the semiconductor chip.

Abstract translation: 半导体芯片安装部件包括适于接合半导体芯片的支撑结构。 支撑结构具有顶表面，底表面和延伸穿过支撑结构的间隙，用于限定支撑结构在间隙的相对侧上的第一和第二部分。 支撑结构包括在支撑结构的第二部分上沿着间隙布置的至少一个细长总线。 支撑结构包括多个导电引线，每个引线具有跨越间隙延伸的连接部分，连接部分具有设置在支撑结构的第一部分上的第一端和固定到总线的第二端。 每个引线包括设置在连接部分的第一和第二端之间的易碎部分，该易碎部分的横截面积小于连接部分的横截面面积。 间隙在支撑结构的底部表面开口。 半导体芯片设置在支撑结构的底表面下方。 引线适于通过断开引线的易碎部分而与半导体芯片上的触点接合，从而将引线的第二端与母线断开，并与半导体芯片的触点接合引线。

公开(公告)号：US5915752A

公开(公告)日：1999-06-29

申请号：US374559

申请日：1995-05-08

Applicant: Thomas H. DiStefano ,  Gary W. Grube ,  Igor Y. Khandros ,  Gaetan Mathieu ,  Jason Sweis ,  Laurie Union ,  David Gibson

Inventor： Thomas H. DiStefano ,  Gary W. Grube ,  Igor Y. Khandros ,  Gaetan Mathieu ,  Jason Sweis ,  Laurie Union ,  David Gibson

IPC: H01L21/60 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/50 ,  H05K1/18 ,  H05K3/36 ,  H05K3/40 ,  H01R43/00

CPC classification number: H01L23/49572 ,  H01L23/3107 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49861 ,  H01L24/01 ,  H01L2924/01082 ,  H01L2924/12042 ,  H05K3/361 ,  H05K3/4084 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49218 ,  Y10T29/49222

Abstract: A connection component for electrically connecting a semiconductor chip to support substrate incorporates a preferably dielectric supporting structure (70) defining gaps (40). Leads extend across these gaps so that the leads are supported both sides of the gap (66, 70). The leads therefore can be positioned approximately in registration to contacts on the chip by aligning the connection component with the chip. Each lead is arranged so that one end can be displaced relative to the supporting structure when a downward force is applied to the lead. This allows the leads to be connected to the contacts on the chip by engaging each lead with a tool and forcing the lead downwardly against the contact. Preferably, each lead incorporates a frangible section (72) adjacent one side of the gap and the frangible section is broken when the lead is engaged with the contact. Final alignment of the leads with the contacts on the chip is provided by the bonding tool which has features adapted to control the position of the lead.

Abstract translation: PCT No.PCT / US93 / 06930 Sec。 371日期1995年5月8日 102（e）日期1995年5月8日PCT提交1993年7月23日PCT公布。 出版物WO94 / 03036 日期1994年2月3日用于将半导体芯片电连接到支撑衬底的连接部件包含限定间隙（40）的优选电介质支撑结构（70）。 引线延伸穿过这些间隙，使得引线被支撑在间隙（66,70）的两侧。 因此，引线可以通过将连接部件与芯片对准而大致对准芯片上的触点。 每个引线被布置成使得当向引线施加向下的力时，一端可相对于支撑结构移位。 这允许引线通过使每个引线与工具接合并将引线向下抵靠接触件而连接到芯片上的触点。 优选地，每个引线包括与间隙的一侧相邻的易碎部分（72），并且当引线与触点接合时，易碎部分断裂。 引线与芯片上的触点的最终对准由具有适于控制引线位置的特征的焊接工具提供。

公开(公告)号：US08997026B1

公开(公告)日：2015-03-31

申请号：US13470080

申请日：2012-05-11

Applicant: Jason Sweis

Inventor： Jason Sweis

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G03F1/70

Abstract: A system and method provide semiconductor fabrication mask creation techniques that align the device features patterned with a first core mask with one or more pad features patterned with a subsequent pad mask. Shapes representing the pad features may be included in the core mask by reducing on all sides, the shape of the pad feature in the core mask by the width of the spacer material. A pad mask then may be created to include a shape of the pad feature that may overlap a portion of the spacer material pattern created by the shape of the pad feature in the core mask. Data sets may be generated from a circuit design to create the masks that may be fabricated with the described techniques.

Abstract translation: 系统和方法提供半导体制造掩模创建技术，其将图案化的设备特征与第一核心掩模对准，其中一个或多个衬垫特征与随后的衬垫掩模图案化。 代表焊盘特征的形状可以通过减少所有侧面，将芯掩模中的焊盘特征的形状减小到间隔物材料的宽度来包括在芯掩模中。 然后可以创建焊盘掩模以包括可以与由芯掩模中的焊盘特征的形状产生的间隔材料图案的一部分重叠的焊盘特征的形状。 可以从电路设计产生数据集以创建可以用所述技术制造的掩模。

公开(公告)号：US5390844A

公开(公告)日：1995-02-21

申请号：US96700

申请日：1993-07-23

Applicant: Thomas H. Distefano ,  Igor Y. Khandros ,  Gaetan Mathiew ,  Jason Sweis ,  John Grange ,  Gary W. Grube

Inventor： Thomas H. Distefano ,  Igor Y. Khandros ,  Gaetan Mathiew ,  Jason Sweis ,  John Grange ,  Gary W. Grube

IPC: H01L21/60 ,  B23K20/02 ,  B23K20/10 ,  H01L21/00 ,  H01L21/603 ,  H05K3/32

CPC classification number: H01L21/67138 ,  B23K20/025 ,  B23K20/106 ,  H01L24/80 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01082

Abstract: A bonding tool for bonding inner leads to semiconductor chips is arranged to capture and align elongated lead sections extending in any one of plural directions, and preferably, in any one of two mutually orthogonal directions. Thus, the tool can be applied to align and bond all of the leads to a chip without turning the tool or the chip even where the leads extend in multiple directions.

Abstract translation: 用于将内部引线键合到半导体芯片的接合工具被布置成捕获和对准沿多个方向中的任一个延伸的细长引线部分，优选地在两个相互正交的方向中的任一个方向上对准。 因此，即使在多个方向上引线延伸的情况下，该工具也可以应用于将所有引线对齐并将其结合到芯片上而不转动工具或芯片。